Electronic-Photonic Design Automation (EPDA)

• EPDA is a comprehensive automation framework integrating device-level simulation, inverse design, and calibration for photonic circuits.
• It employs hierarchical, machine-readable representations and GPU-accelerated placement to optimize routing, reduce insertion loss, and enhance manufacturability.
• EPDA streamlines yield optimization through differentiable legalizers and agent-driven iterations, enabling scalable and sustainable photonic ecosystem designs.

Electronic-Photonic Design Automation (EPDA) denotes a full-lifecycle, cross-layer design automation stack for electronic-photonic integrated circuits and photonic AI systems, spanning device-/circuit-level simulation, architecture-level modeling, component inverse design, chip/layout automation, and closed-loop co-optimization across these layers (Zhu et al., 12 Apr 2026). In parallel, it is framed as the automation layer needed to make electronic-photonic integrated circuits practical, scalable, and sustainable, because manual flows do not scale to systems whose behavior depends simultaneously on device physics, circuit topology, routing, memory, dataflow, manufacturability, and calibration (Yin et al., 9 Sep 2025).

1. Historical emergence and scope

An early photonic design automation tool embedded photonic layout generation directly into Cadence/Virtuoso through SKILL, enabling seamless integration of photonic and electronic design in a single environment (Alloatti et al., 2015). That tool addressed advanced CMOS nodes such as 45 nm SOI, where photonic devices had to coexist with large-scale electronic circuits while satisfying 10,000 to 50,000 design rules. It introduced technology-independent “photonic” design levels, custom waveguide ports, auto-routing of waveguide connections, and a system-level flow in which DRC cleanup occurs after placement, not merely at isolated device level (Alloatti et al., 2015).

This early stage already established several durable EPDA themes. First, photonic design could not be reduced to ordinary electronic layout editing, because photonic objects carry optical intent, port orientation, and process-specific exclusion semantics. Second, manufacturability had to be automated rather than repaired manually. Third, electronic-photonic co-design required a shared CAD environment rather than disconnected optical and electrical tools (Alloatti et al., 2015).

Later literature generalized EPDA from a layout-centric capability into a broad systems discipline. The field now treats EPDA as the missing infrastructure connecting simulation, inverse design, architecture modeling, physical implementation, and back-annotation, with the explicit goal of moving from laboratory prototypes to a scalable, reproducible electronic-photonic ecosystem (Zhu et al., 12 Apr 2026). A notable correction to a common misconception follows from this progression: EPDA is not only a photonic analogue of digital place-and-route; it is a cross-layer methodology whose targets include manufacturability, calibration, workload mapping, and system-level realism.

2. Core abstractions and modeling layers

A defining feature of EPDA is the replacement of ad hoc photonic scripting with explicit machine-readable representations. In SimPhony, the central abstraction is a hierarchical, netlist-based representation of photonic circuits using directed 2-pin nets rather than undirected multi-pin electrical nets, because optical signal flow is directional. A minimal functional block is defined as a node, larger circuits are assembled hierarchically, and the result is a weighted directed acyclic graph (DAG) used for critical-path extraction, insertion-loss propagation, link-budget analysis, and layout-aware area estimation (Yin et al., 2024). This representation supports both dynamic array-style architectures such as TeMPO and static mesh-style architectures such as Clements-style MZI meshes (Yin et al., 2024).

At the physical-layout layer, LiDAR 2.0 introduces a YAML-based PIC intermediate representation, explicitly inspired by LEF/DEF, to capture photonic components, connectivity, hierarchy, and module reuse (Zhou et al., 22 May 2025). In agentic design workflows, PhIDO uses a YAML-based DSL compatible with GDSFactory, where components are encoded as nodes, interconnects as edges, and the representation also stores component parameters, PDK selection, wavelength band, port types, and metadata (Sharma et al., 18 Aug 2025). This suggests that EPDA is converging on formal interchange layers that decouple specification, schematic intent, and physical realization.

Compact-modeling and co-simulation form the complementary abstraction layer. A data-driven Eigenmode Propagation Method (DEPM) represents linear passive devices through a Hamiltonian built from intrinsic waveguide parameters extracted via complex coupled-mode theory, yielding millisecond-scale simulations within the model’s valid scope and enabling rapid tolerance analysis and wavelength sweeps (Zhang, 12 Jan 2025). At circuit level, electro-optic co-simulation has been moved into standard electronic simulators by expressing photonic devices as interoperable Verilog-A compact models. Using a baseband-equivalent optical representation, an optical link testbench was validated against experiment up to 64 Gbaud, with models including optical losses, back-reflection, nonlinearity, high-frequency response, and noise (Kawahara et al., 2024). The resulting EPDA picture is not a single tool but a stack of interoperable abstractions: graph-level circuit intent, compact device models, and physical-layout representations.

3. Placement, routing, and physical implementation

Modern EPDA treats photonic physical design as a first-class optimization problem rather than a schematic afterthought. In placement, Apollo is described as the first GPU-accelerated, routing-informed placement framework for large-scale PICs (Zhou et al., 26 Apr 2025). Its objective,

$$\mathcal{L}(x, y) = \textrm{cosWA}(x, y) + \lambda_{NS} \cdot NS(x,y) + \mathcal{D}(x, y),$$

combines an asymmetric bending-aware wirelength surrogate, a routing-informed net spacing model, and an electrostatic density term (Zhou et al., 26 Apr 2025). Across all benchmarks, Apollo reports a geometric-mean routing success rate of 94.79% with 48.72 s geometric-mean runtime, compared with 50.85% for DREAMPlace+RO and 51.38% for Cypress (Zhou et al., 26 Apr 2025). The significance is straightforward: in PICs, placement quality is largely determined by whether routing will later be physically legal.

Detailed routing required a parallel rethinking. APR and later LiDAR formalize routing as geometry-aware search over curvilinear waveguides, with explicit handling of minimum bend radius, port orientation, waveguide spacing, crossing legality, and insertion loss (Zhou et al., 2024). Their routing objective is not merely path length. Instead,

$$IL(p_i)=\sum_{m_j\in p_i}IL(m_j)+\sum_{n_j\in p_i}IL(n_j),$$

with route loss decomposed into propagation, crossing, and bend terms; the global target is

$IL_{max} = \max_{p_i \in P} IL(p_i).$

APR reports DRV-free layouts on all benchmarks, 14% lower average critical-path insertion loss, and 6.25× speedup over the baseline on average (Zhou et al., 2024).

LiDAR 2.0 extends this to hierarchical routing with sub-circuit reuse, redundant-bend elimination, crossing space preservation, and routing-order refinement (Zhou et al., 22 May 2025). On spacious layouts it reports up to 16% lower insertion loss and 7.69× speedup over prior methods, while on compact layouts it reports 9% lower insertion loss and 6.95× speedup over LiDAR 1.0 (Zhou et al., 22 May 2025). A common misconception is that photonic routing is simply “electronic routing with curves.” These results show otherwise: same-layer crossings are allowed but must be inserted physically, port access is directional, and routing quality is dominated by optical loss rather than only congestion.

For active PICs, physical implementation also includes metal interconnect. A planning-guided automated electrical router introduces a physically-aware global planner, sequence-consistent track assignment, and soft guidance-assisted detailed routing that explicitly consume previously routed waveguides and photonic keep-outs (Zhou et al., 28 Sep 2025). Across large active PIC designs, it reports about 99% reduction in via count, about 98% reduction in user-specified design rule violations, and about 17× runtime speedup on average (Zhou et al., 28 Sep 2025). EPDA therefore includes both waveguide routing and photonics-aware electrical routing within one physical-design stack.

4. Inverse design, legalization, and yield optimization

Inverse design introduced a new EPDA problem: highly compact devices could be optimized electromagnetically yet remain difficult to fabricate or integrate. ADEPT addressed one part of this problem by turning photonic tensor-core topology search into a differentiable EPDA task, jointly optimizing depth, routing permutations, and coupler placement under explicit footprint constraints (Gu et al., 2021). Across benchmarks, searched topologies achieved competitive matrix representability, 2-30x higher footprint compactness, and better noise robustness than prior manually designed structures (Gu et al., 2021). This established automated topology synthesis as an EPDA function rather than a manual circuit-design exercise.

At device-and-layout scale, PoLaRIS unifies BOSON and MAPS for fabrication-aware inverse design with Apollo and LiDAR for system-level placement and routing, targeting DRV-free, performance-optimized layouts for PICs with hundreds to thousands of components (Zhou et al., 30 Jul 2025). Its importance lies in coupling physics-aware device synthesis with layout-rule-aware implementation. A plausible implication is that EPDA is moving from stagewise optimization toward flows in which device synthesis and physical layout are co-designed from the outset.

Manufacturability required an additional stage beyond inverse design. OptiClear defines an explicit post-design legalization stage for EPDA for curvilinear inverse-designed photonic devices (Zhou et al., 3 Jul 2026). It operates directly on the pixelated mask using morphology:

$$Open(M) = Dilate(Erode(M)), \qquad Close(M) = Erode(Dilate(M)).$$

The legalizer seeks masks that satisfy the stationary condition

$M = Open(M) = Close(M).$

Two engines are provided: OptiClear-R, a rule-based morphological legalizer, and OptiClear-D, a differentiable legalizer formulated as a minimum-distortion mask optimization problem (Zhou et al., 3 Jul 2026). Across diverse inverse-designed devices and design-rule settings, both engines reduce design-rule violations from thousands to zero, while the differentiable version more faithfully preserves optical functionality (Zhou et al., 3 Jul 2026). This directly corrects another misconception: fabrication-aware inverse design alone, with soft penalties on small features and curvature, does not guarantee final DRC compliance.

The most comprehensive yield-native flow is OptoSynthesizer, which integrates OptoSynthesizer-InvDes, OptoSynthesizer-Place, and OptoSynthesizer-Route into an end-to-end physical design automation flow for yield-optimized, inverse-designed EPICs (Zhou et al., 16 Apr 2026). It packages robust inverse-designed devices as PDK cells, applies photonics-aware inverse lithography through PRISM, performs routing-informed placement and hierarchical optical/electrical routing, and then evaluates post-layout and post-fabrication behavior (Zhou et al., 16 Apr 2026). Reported case studies include yield improvements to nearly 90% or higher for several inverse-designed devices, more than 1,000 components in about 100 seconds during placement, and more than 8,000 nets in 425 seconds during routing (Zhou et al., 16 Apr 2026). Here EPDA becomes explicitly yield-aware rather than only geometry-aware.

5. Cross-layer co-design, co-simulation, and calibration

A major branch of EPDA focuses on system modeling rather than only geometry synthesis. SimPhony is presented as a cross-layer modeling and simulation framework for heterogeneous EPIC AI systems, spanning SimPhony-DevLib, SimPhony-Arch, and SimPhony-Sim (Yin et al., 2024). It supports generic, extensible hardware topology representation, optics-specific dataflow modeling with multi-dimensional parallelism and reuse, data-aware energy modeling with realistic device responses, layout-aware area estimation, link-budget analysis from critical-path optics, bandwidth-adaptive memory modeling, and hardware/software co-simulation (Yin et al., 2024). One concrete result is that layout-unaware methods can underestimate node area by 72%, underscoring why EPDA must include layout realism even at architecture-exploration stage (Yin et al., 2024).

Open-source EPDA roadmaps extend this further. A cross-layer co-design framework organized around SimPhony, NeurOLight, PACE, PIC$^2$O-Sim, MAPS, and SP$^2$RINT argues that EPDA should be open-source, AI-augmented, cross-layer, and fabrication-aware, with eventual push-button arch-to-layout automation (Zhou et al., 31 Dec 2025). The same perspective emphasizes that electromagnetic simulation is often too slow, device design remains heuristic/manual, and hardware non-idealities are weakly coupled to AI-level metrics unless a unified automation stack is available (Zhou et al., 31 Dec 2025).

EPDA also includes control and calibration for analog photonic hardware. In resonator weight banks, practical deployment requires automation across device physics, fabrication variation, control electronics, sensing circuitry, and system-level inference performance (Lima et al., 2022). The reviewed workflow distinguishes feedforward calibration from embedded-sensor feedback control, models thermal crosstalk through a matrix $\mathbf{K}$, and treats sensing and actuation choices as design variables rather than external operating assumptions (Lima et al., 2022). This broadens the scope of EPDA beyond layout and routing: in analog photonic systems, calibration and disturbance rejection are part of the design-automation problem.

6. AI-generated and agentic EPDA

LLMs and agentic systems have recently been positioned as an additional EPDA layer, but the literature is careful about both capability and limitation. PICBench is the first open-source benchmark and evaluation framework for using LLMs to generate PIC designs, with 24 carefully designed PIC problems, expert-written golden solutions, simulation-based functional checking in SAX, and Pass@1/Pass@5 evaluation (Wu et al., 5 Feb 2025). The benchmark shows that restrictions help a lot, feedback helps a lot, and that current models can often learn structural patterns of PIC netlists while still struggling with domain-specific correctness and functional validity (Wu et al., 5 Feb 2025). This makes one point unambiguous: contemporary LLMs are not yet reliable one-shot PIC designers.

PhIDO extends the ambition from netlist generation to natural-language photonic integrated circuit design requests into layout mask files through a four-stage multi-agent pipeline: Interpreter, Designer, Layout, and Circuit verification (Sharma et al., 18 Aug 2025). Tested on 102 design descriptions ranging from single devices to 112-component PICs, it reports up to 91% success rate for single-device designs, while for queries with less than or equal to 15 components, o1, Gemini-2.5-pro, and Claude Opus 4 achieve the highest end-to-end pass@5 success rates of approximately 57% (Sharma et al., 18 Aug 2025). The paper explicitly frames the endpoint as structural validity, not fabrication sign-off with a commercial PDK/DRC deck (Sharma et al., 18 Aug 2025).

A more ambitious direction is agent-driven propose → simulate → evaluate → iterate design (Kharel et al., 30 May 2026). In one routing/layout demonstration, an agent working with PhotonForge reduced an initial 192 DRC violations—including 30 heater cut-throughs and 162 route crossings—to 0 after 27 iterations, with runtime 2 minutes 25 seconds, whereas a human engineer typically needs 2–3 hours on the same chip (Kharel et al., 30 May 2026). The same framework also demonstrated passive-device design, active-device junction exploration, RF electrode design, and an integrated silicon photonic modulator workflow (Kharel et al., 30 May 2026). Taken together, these results suggest that agentic EPDA is best viewed as orchestration over simulators, rules, and verification loops, not as a replacement for the underlying physical-design and modeling stack.

7. Outlook and unresolved directions

Recent reviews place EPDA at the center of a roadmap from prototypes to scalable, reproducible electronic-photonic ecosystems, emphasizing future needs such as co-packaged optics, multi-layer / 3D photonics, LVS and signoff beyond geometric DRC, and post-layout back-annotation for system co-simulation (Zhu et al., 12 Apr 2026). This suggests that current EPDA flows, while increasingly end-to-end, still stop short of the full signoff and interoperability maturity long associated with advanced electronic EDA.

Sustainability perspectives add another axis. EPDA is described as a sustainability enabler because it can systematically optimize placement and routing solutions to generate more compact layouts for large-scale EPICs and use fewer routing layers, thereby reducing die area, manufacturing complexity, and embodied carbon footprint (Yin et al., 9 Sep 2025). In this view, compact placement and routing are not merely geometric optimizations; they are lifecycle optimizations.

Several technical gaps are already identified by the literature itself. OptiClear explicitly points toward future end-to-end design-rule-aware inverse design, where legalization and synthesis are integrated rather than treated separately (Zhou et al., 3 Jul 2026). OptoSynthesizer makes clear that broader foundry support, richer device libraries, and stronger standard benchmarks remain necessary for standardized, reproducible, yield-native EPDA (Zhou et al., 16 Apr 2026). A plausible implication is that the next phase of EPDA will be defined less by isolated tools than by how completely these tools share representations, back-annotate physical effects, and close the loop from specification to fabrication-ready, calibrated, and workload-validated systems.