Panel-Scale Reconfigurable Photonic Interconnects

• Panel-scale reconfigurable photonic interconnects are large-area optical fabrics that leverage programmable nodes and tunable couplers to dynamically route signals between chiplets, accelerators, or servers.
• They incorporate diverse architectures—including glass-substrate crossbars, silicon photonic meshes, and MEMS-based Benes networks—to balance insertion loss, power consumption, and reconfiguration latency.
• Advanced control techniques such as program-and-verify and FPGA-driven tuning optimize reconfiguration trade-offs, enabling efficient collective scheduling for high-bandwidth optical communication.

Searching arXiv for the cited work and closely related papers on programmable and panel-scale photonic interconnects. Panel-scale reconfigurable photonic interconnects are large-area optical communication fabrics in which optical paths are altered by programmable switch nodes, tunable couplers, or nonvolatile photonic gates to connect chiplets, accelerators, or servers across a shared substrate or tiled assembly. Across recent work, the term encompasses glass-substrate photonic interposers up to $500\text{-mm}\times500\text{-mm}$ or larger, panels of $N$ accelerators that share a reconfigurable photonic fabric as one scale-up domain, and silicon-photonic programmable meshes whose projected panel-scale footprint includes a $100\,\text{mm}\times100\,\text{mm}$ patch with $\approx25\,000$ gates (Hsueh et al., 8 Aug 2025, Addanki, 9 Oct 2025, Chen et al., 23 Jun 2025).

1. Architectural forms and network organization

Several distinct architectural families recur in the literature. One is the planar crossbar on a glass substrate, implemented as a two-layer waveguide fabric with a horizontal layer $H$ and a vertical layer $V$, where each $H$–$V$ crossing contains a vertically-coupled add-drop racetrack resonator pair that functions as a $2\times2$ optical switch node. In that formulation, the number of switch nodes is

$M = N_h \times N_v,$

and a multilayer extension uses

$N$0

This architecture is explicitly presented as panel-edge-to-panel-edge routing on a glass photonic interposer without active repeaters, while remaining compatible with commercial processor chiplets and $N$1 HBM stacks (Hsueh et al., 8 Aug 2025).

A second family is the programmable silicon-photonic mesh. In "NEO-PGA: Nonvolatile electro-optically programmable gate array" (Chen et al., 23 Jun 2025), the basic unit cell is an MZI gate composed of two $N$2 MMIs and two Sb$N$3Se$N$4-clad arms on silicon waveguides. Two mesh organizations are distinguished. The circulating rectangular mesh functions as an optical circuit switch and can be reconfigured into ring resonators, dual-ring systems, and coupled-cavity arrays. The forward-only Clement-style mesh functions as a self-configurable PIC that progressively learns to sort two orthogonal beams.

A third family uses discrete switching stages. The $N$5 Benes network based on $N$6 split waveguide crossing MEMS switches contains $N$7 stages for $N$8, with $N$9 switch cells per stage and $100\,\text{mm}\times100\,\text{mm}$0 total cells (Hu et al., 2023). Earlier work on microring switching organized an $100\,\text{mm}\times100\,\text{mm}$1 fabric from $100\,\text{mm}\times100\,\text{mm}$2-to-$100\,\text{mm}\times100\,\text{mm}$3 demultiplexers and $100\,\text{mm}\times100\,\text{mm}$4-to-$100\,\text{mm}\times100\,\text{mm}$5 multiplexers, enforcing path-independent insertion loss by a fixed demux-to-mux connectivity rule (Nikolova et al., 2015).

These architectures differ in switching physics, loss accumulation, and control strategy, but they share a common systems role: they create reconfigurable optical connectivity that can either emulate direct matchings for collective communication or implement fixed-depth routing fabrics with large port count.

2. Switching primitives, materials, and physical operating principles

The physical switch primitive strongly determines static power, reconfiguration speed, bandwidth, and layout density. In the NEO-PGA platform, the phase-change section is $100\,\text{mm}\times100\,\text{mm}$6 Sb$100\,\text{mm}\times100\,\text{mm}$7Se$100\,\text{mm}\times100\,\text{mm}$8 on a $100\,\text{mm}\times100\,\text{mm}$9 wide $\approx25\,000$0 long Si ridge, capped by $\approx25\,000$1 Al$\approx25\,000$2O$\approx25\,000$3, and driven by a PIN-diode microheater located $\approx25\,000$4 from the waveguide with zero static loss. Sb$\approx25\,000$5Se$\approx25\,000$6 is described as a wide-bandgap phase-change material with amorphous $\approx25\,000$7, $\approx25\,000$8, and crystalline $\approx25\,000$9, $H$0, giving $H$1. The induced phase shift follows

$H$2

and the MZI splitting ratio is controlled by

$H$3

The same work reports MZI insertion loss $H$4 total and extinction ratio up to $H$5 (Chen et al., 23 Jun 2025).

The glass-panel crossbar instead uses thermally tuned resonant switch nodes. Each vertically-coupled add-drop racetrack resonator can be set to “pass-through” or “turn,” with $H$6 bypass loss, $H$7 turn loss, and off-state extinction $H$8. The path loss model is

$H$9

and for the stated worst-case $V$0 edge-to-edge route in an $V$1 array of unit-interposers the estimate is $V$2 (Hsueh et al., 8 Aug 2025).

Microring-based switching provides another resonant mechanism. In the $V$3 silicon photonic switch fabric, a change in applied voltage produces a temperature shift and a resonance displacement

$V$4

with $V$5, and $V$6 across the heater shifts the ring by one free spectral range of $V$7. Through-port and drop-port transmission are modeled in terms of round-trip attenuation $V$8 and self-coupling $V$9, with extracted values $H$0 and $H$1 (Nikolova et al., 2015).

The MEMS split-waveguide-crossing switch is nonresonant and mechanically reconfigures the crossing geometry. Its OFF state is represented by

$H$2

and its ON state by

$H$3

with $H$4 and residual bar-coupling $H$5. The switch region is $H$6, the total device footprint is $H$7, and the measured bandwidth spans $H$8 (Hu et al., 2023).

Taken together, these platforms illustrate the principal design trade-off. Volatile thermo-optic tuning is mature but incurs static power and thermal-management overheads. Nonvolatile phase-change meshes target $H$9. MEMS switches target sub-$V$0 average power and ultrawide optical bandwidth. Resonant glass-panel crossbars emphasize very large-area reach and WDM density.

3. Programming, calibration, and control planes

Programming methods range from analog, closed-loop multibit tuning to binary switching and topology-level scheduling. The NEO-PGA platform uses a closed-loop “program-and-verify” method with bidirectional, progressive tuning by partial amorphization and crystallization. After each pulse, a monitor reads output power and adjusts the next pulse amplitude until the target is within $V$1. Typical pulse conditions are $V$2, $V$3 for amorphization and $V$4, $V$5 for crystallization, with programming energy $V$6 for amorphization and $V$7 for crystallization. Because the PCM is nonvolatile, the mesh is explicitly described as “set-and-forget,” and adjacent gates remain undisturbed with localized switching to $V$8 (Chen et al., 23 Jun 2025).

The forward-only NEO-PGA mesh also introduces a self-configurable mode. In that case, a two-stage MZI network progressively tunes itself to route two orthogonal input vectors $V$9 to outputs $2\times2$0. This is not merely static circuit programming; it is a local closed-loop adaptation procedure embedded in the photonic fabric itself (Chen et al., 23 Jun 2025).

Microring fabrics use firmware-controlled heater biasing. The $2\times2$1 switch employs a Stratix V FPGA with DAC controllers, an embedded NIOS microprocessor, and an RTL scheduler that sequences ring bias updates to achieve simultaneous multi-ring tuning. The stated path-setup flow consists of request receipt, ring-index lookup, DAC writes, thermal settling over roughly $2\times2$2, optional monitor-photodiode verification, and routing-table update. Demonstrated path-to-path reconfiguration used hold times of $2\times2$3 and $2\times2$4, with total cycle $2\times2$5 (Nikolova et al., 2015).

MEMS Benes fabrics require high-voltage actuation and pad-count reduction. The proposed control path is FPGA $2\times2$6 level-shifter array $2\times2$7 HV comb-drive drivers $2\times2$8 $2\times2$9 comb electrodes, with direct row/column addressing used to avoid conventional $M = N_h \times N_v,$0 pads. Calibration provisions include built-in monitor photodiodes, automated OSA sweeps per die, and digital binary ON/OFF thresholds (Hu et al., 2023).

At the panel and scale-up-domain level, the control plane becomes a synchronization problem. One proposal assumes a lightweight control plane that synchronizes barrier and reconfiguration across a shared-memory domain, while the theory of adaptive photonic scale-up domains makes reconfiguration itself a schedule decision variable rather than a fixed overhead (Addanki, 9 Oct 2025).

4. Communication-theoretic models and the reconfiguration decision

A central question is whether a reconfigurable photonic fabric should actually be reconfigured for a given communication step. In adaptive photonic scale-up domains, the system model uses $M = N_h \times N_v,$1 endpoints, link bandwidth $M = N_h \times N_v,$2, reconfiguration delay $M = N_h \times N_v,$3, and a base topology $M = N_h \times N_v,$4. A collective is written as a sequence of matchings $M = N_h \times N_v,$5 with volumes $M = N_h \times N_v,$6, and the aggregate demand matrix is

$M = N_h \times N_v,$7

Per-step completion time is

$M = N_h \times N_v,$8

where $M = N_h \times N_v,$9 is the maximum concurrent-flow factor. Total completion time is

$N$00

This places propagation delay, congestion, and reconfiguration overhead in one latency model rather than treating circuit switching as cost-free (Addanki, 9 Oct 2025).

The same framework connects collective scheduling to Birkhoff–von Neumann decomposition. In pure form,

$N$01

while in collectives

$N$02

is already a weighted decomposition into permutation matrices. The immediate systems interpretation is that naive reconfiguration before every step realizes one-hop, full-rate paths for each matching, but also incurs the full $N$03 penalty at every step (Addanki, 9 Oct 2025).

The optimization criterion is therefore conditional. The stated heuristic threshold is to switch when

$N$04

This formalizes a common misconception in discussions of photonic collectives: it is not generally optimal either to reconfigure before every matching or never to reconfigure. The simulation study reports a transitional diagonal regime in which an optimized schedule outperforms both extremes by up to $N$05 (Addanki, 9 Oct 2025).

For all-to-all, the optimization problem is recast at a different abstraction level. Any candidate sequence of topologies and flow schedules can be written as

$N$06

where $N$07 is the all-to-all traffic matrix, $N$08 are topology adjacency matrices, and $N$09 are hop counts. For $N$10, $N$11 nodes, and exactly $N$12 reconfigurations, the lower bound is

$N$13

with $N$14 and $N$15. This work explicitly criticizes assumptions under which it is never or always worthwhile to reconfigure, and reports up to $N$16 reduction in all-to-all completion time on average across a wide range of network parameters, message sizes and workload types (Zhou et al., 11 Feb 2026).

5. Demonstrated systems and representative metrics

The experimental literature spans nonvolatile photonic meshes, microring switch fabrics, MEMS Benes networks, and large-area glass interposers. The reported functions are not interchangeable: some platforms prioritize low-loss broadband switching, others self-configuration or coupled-cavity programmability, and others end-to-end panel reach or large-port-count spatial switching.

Platform	Demonstrated function	Representative metrics
NEO-PGA	$N$17 OCS, high-$N$18 resonators, self-configurable beam sorting	$N$19 routings; crosstalk $N$20; $N$21; beam-sorting crosstalk $N$22
Microring $N$23 fabric	Fully non-blocking silicon photonic switch	path IL $N$24; thermal tuning $N$25
SWX MEMS $N$26 Benes	High-port-count switch array	ON $N$27; OFF $N$28; ON $N$29, OFF $N$30
Glass-panel WDM crossbar	Panel-edge-to-panel-edge interconnect	$N$31 measured IL; $N$32 crosstalk; $N$33; $N$34

Within NEO-PGA, the circulating mesh is used as a broadband optical circuit switch over $N$35 with $N$36 routings and crosstalk $N$37. The same mesh realizes programmable ring resonators with $N$38 up to $N$39 and $N$40 for a $N$41 loop, plus dual rings with independent tuning and a coupled-cavity strong-to-weak coupling transition. The forward mesh sorts two orthogonal input vectors with crosstalk $N$42, and $N$43 in best cases (Chen et al., 23 Jun 2025).

The $N$44 microring switch demonstrates a path-independent loss rule in which every path traverses exactly $N$45 bar rings plus $N$46 cross rings, giving $N$47 rings for $N$48. The resulting end-to-end insertion loss is measured at $N$49 after polarization and resonance fine tuning, and the power penalty remains $N$50 at $N$51 with six decorrelated crosstalk sources (Nikolova et al., 2015).

The MEMS split-waveguide-crossing switch reports OFF-state excess loss $N$52, ON-state excess loss $N$53, OFF-state crosstalk $N$54, ON-state crosstalk $N$55, threshold drive $N$56, dynamic energy $N$57, steady-state power $N$58, and durability $N$59 cycles. The associated $N$60 Benes network is presented as a practical route to panel-scale interconnect and routing (Hu et al., 2023).

For the glass-panel interposer, the stated WDM parameter set uses $N$61 wavelengths, $N$62, and $N$63, giving $N$64 per waveguide. The measured metrics listed for the $N$65 scale are $N$66 insertion loss, $N$67 total crosstalk, $N$68, and $N$69, with a scaling estimate of $N$70 insertion loss when moving from $N$71 to $N$72 (Hsueh et al., 8 Aug 2025).

6. Scaling limits, packaging strategies, and unresolved issues

Scaling is constrained by gate density, loss accumulation, addressing granularity, and control latency. For the PCM-programmable MZI mesh, the gate footprint is $N$73, corresponding to $N$74 gates/$N$75 and $N$76 nodes/$N$77 when both arms are counted. The same estimate yields $N$78 programmable gates on a $N$79 wafer and $N$80 gates on a $N$81 panel-scale patch. However, total on-board reconfiguration time is stated to be limited by serial pulse addressing, with $N$82 gates $N$83 for full-panel reconfiguration unless parallel drivers or multiplexed addressing are introduced (Chen et al., 23 Jun 2025).

For resonant crossbars on glass, the principal limit is accumulated route loss rather than static-programming energy. The worst-case $N$84 path is modeled at $N$85, supported without active repeaters by injecting $N$86 per carrier, while doubling panel dimension to $N$87 increases insertion loss by $N$88 and reduces bandwidth density by a factor of four. Thermal behavior is treated locally, with adjacent-node thermal crosstalk $N$89, panel-level fiducials and passive stops achieving $N$90 lateral and $N$91 vertical alignment, and edge couplers tolerating $N$92 gap variation for $N$93 efficiency (Hsueh et al., 8 Aug 2025).

For MEMS Benes networks, the panel-scale roadmap is explicitly modular. A $N$94 die is $N$95; a $N$96 panel can be organized as a $N$97 array of $N$98 dies, or a $N$99 array if each $100\,\text{mm}\times100\,\text{mm}$00 is folded. Proposed packaging elements include edge couplers plus low-loss polymer interposers across die boundaries, fiber-array interfaces or free-space microlens-array coupling, and hermetic metal packages with $100\,\text{mm}\times100\,\text{mm}$01 pins per die (Hu et al., 2023).

At the systems level, the unresolved issues are increasingly algorithmic. The adaptive-scale-up literature identifies the need for fast online heuristics approximating dynamic programming in $100\,\text{mm}\times100\,\text{mm}$02 or $100\,\text{mm}\times100\,\text{mm}$03, lightweight proxies for $100\,\text{mm}\times100\,\text{mm}$04, models with variable $100\,\text{mm}\times100\,\text{mm}$05, overlap between compute and reconfiguration, and multi-ported fabrics that support unions of multiple matchings per step. The all-to-all literature adds hierarchical local/global scheduling, staggered OSW pipelines to hide $100\,\text{mm}\times100\,\text{mm}$06, fall-backs for latency-sensitive mice flows, and multi-tenant isolation through time slots or disjoint wavelength sets (Addanki, 9 Oct 2025, Zhou et al., 11 Feb 2026).

A plausible implication is that “panel scale” is not a single hardware category but a co-design regime. The physical fabric, the programming mechanism, and the collective scheduler are coupled: low-static-power nonvolatile meshes reduce standby cost, MEMS and microrings offer different reconfiguration-delay regimes, and large-area WDM crossbars shift the bottleneck toward insertion loss and control orchestration rather than only switch count.