PhIDO: Photonics Intelligent Design & Optimization

• PhIDO is a multi-agent AI framework that converts natural language photonic integrated circuit requests into fabrication-ready physical layouts.
• It employs coordinated modules (Interpreter, Designer, Layout, and Verification) to ensure accurate entity extraction, schematic generation, and error checking.
• Benchmarking on 102 design queries highlights high success for simple devices while identifying challenges in error propagation and PDK coverage for complex circuits.

Photonics Intelligent Design and Optimization (PhIDO) refers to a multi-agent AI architecture developed to automate the translation of natural-language photonic integrated circuit (PIC) design requests into foundry-ready physical layout files. The framework represents a convergence of instruction-tuned LLMs, domain-specific design languages, structured process design kit (PDK) data, and procedural layout/simulation tools, forming an end-to-end path from user intent to mask fabrication. PhIDO was demonstrated on a testbench of 102 design queries spanning from single stand-alone devices to circuits containing over 100 components, and enabled benchmarking of several state-of-the-art LLMs for reasoning and PIC design tasks (Sharma et al., 18 Aug 2025).

1. Framework Architecture

PhIDO consists of four primary modules operating in a coordinated pipeline:

1. Interpreter Agent: Parses free-form natural language queries, extracts entities (functional blocks, interconnectivity, constraints), and assembles an early-stage “PIC template.” It uses entity extraction, schema validation (via Pydantic), and retrieval from a circuit template library to structure the design intent into YAML-formatted records.
2. Designer Agent: Resolves each abstract block and connection in the template into candidate PDK (Process Design Kit) components. The agent assigns or infers parameter values (e.g., waveguide width, radii, phase shifter voltages), and generates a detailed schematic using a domain-specific YAML-based DSL, with explicit port-to-port connectivity.
3. Layout Agent: Consumes the schematic and generates a physical GDSII layout. The placement uses graph-based algorithms (notably DOT from Graphviz for component distribution) and GDSFactory’s river router for constraint-aware optical and electrical interconnects.
4. Circuit Verification: Simulates the generated layout using tools such as the SAX circuit simulator, providing checks for design rule adherence and basic performance metrics to flag errors or yield warnings for further review.

The system translates a natural-language user prompt through these four modules, successively converting it into a machine-interpretable schematic and finally to a mask file suitable for fabrication.

2. AI Agents and Task Decomposition

PhIDO’s core intelligence is distributed between its two main AI agents—the Interpreter and the Designer—both built on instruction-tuned LLMs and using retrieval augmentation strategies. The processing steps are as follows:

• The Interpreter Agent receives the user’s query, extracts functional and parametric entities using schema-enforced prompts, and builds a hierarchical template for the circuit. It searches a library of known design topologies, supporting reuse and adaptation of prior work.
• The Designer Agent maps each block in the template to one or more specific PDK cells, using a qualitative ranking system (“exact,” “partial,” or “poor” match) and integrates parametric information (including special constraints such as phase-length control). It constructs a complete, connection-resolved schematic.

Outputs from both agents are syntactically and semantically validated at each stage, with fallback re-query steps for error correction—this reduces both hallucination and propagation of structural errors.

3. Performance Evaluation and Metrics

PhIDO’s efficacy was quantified through systematic testing on 102 diverse PIC design queries, ranging in complexity from single elements to 112-component circuits. Evaluation metrics included:

• Absolute Occurrence Rate: Proportion of test cases (for a given model) failing or succeeding at each sequential stage, including early attrition due to unparseable or incomplete outputs. Defined as

$$\text{Absolute Occurrence}_{(r,m)} = \frac{N_{(r,m)}}{N_\text{total}}$$

• Conditional Occurrence Rate: Probability of an error or success at a given stage $st$, conditional on a design successfully reaching $st$ (hence removing attrition bias from earlier failures). Formally,

$$\text{Conditional Occurrence}_{(r,st,m)} = \frac{N_{(r \text{ at } st, m)}}{N_\text{total} - \sum_{i \in \text{prior}(st)} N_{(r \text{ at } i, m)}}$$

• Aggregate Success (pass@1, pass@5): Fraction of trials with a successful final layout, with up to 5 response attempts allowed per model (pass@5).

Single-device designs (Level 1) showed success rates up to 91%; for circuits with ≤15 components, top models reached end-to-end pass@5 rates of ~57%.

4. Benchmarking and Model Comparison

Seven LLMs were benchmarked, including OpenAI’s o1 and o3-mini, Google’s Gemini-1.5-pro and Gemini-2.5-pro, Anthropic’s Claude Opus 4, DeepSeek’s R1, and Nvidia’s Nemotron Ultra-253B. Results included:

• Gemini-2.5-pro: Provided the strongest balance between accuracy and computational cost, with pass@5 rates ≈58% for moderate-complexity designs, and required the least output tokens. Demonstrated robustness even for large-scale (>15 component) queries.
• Claude Opus 4: Comparable to Gemini-2.5-pro; “extended thinking” mode reduced schematic and parameter errors, though at higher cost.
• o1: Showed high accuracy on simple designs but was less efficient in terms of output length/cost.
• Less effective models (o3-mini, DeepSeek-R1, Nemotron): Higher error rates especially for schematic generation and parameter assignment phases, with schematic generation errors up to 60% (Nemotron); struggled on higher complexity tasks.

Key error modes included schematic generation failure and unsatisfied parameter constraints, with most stage attrition observed at the entity extraction and schematic construction stages for highly complex (>15 components) prompts.

5. Design Workflow, Knowledge Representation, and Standardization

The design flow orchestrates a staged transformation from human intent to foundry-ready layout:

1. User query in natural language → entity extraction into a structured, schema-validated YAML template
2. Component mapping/parameterization → schematic in DSL form
3. Automated placement and routing → GDSII mask file
4. Simulation and rule checking → performance/DRC report

Each agent’s outputs are structured using standardized intermediate representations, enabling programmatic parsing, validation, and seamless hand-off. Domain-specific language (DSL) schema and Pydantic-enforced validation are central for robust knowledge representation, with fallback/failure modes managed by error detection and re-query strategies.

Future standardization—of intermediate DSL, data models, and communication protocols between agents—was identified as essential for reproducibility, benchmarking, and modular system evolution.

6. Limitations and Prospective Developments

Despite robust performance on simple designs, current limitations include:

• Error propagation and attrition bias: Early-stage failure (e.g., entity extraction) limits recoverability for complex requests.
• Dataset and PDK coverage: Larger, more diverse design and component corpora are needed to improve accuracy and accommodate novel topologies and parameter regimes.
• Verification and closure-of-loop: Present verification modules provide basic DRC and performance checking; integration of advanced simulation, physical optimization, and hardware-in-the-loop feedback remains future work.
• Robotic and experimental automation: Extending the framework to close the design/fabrication/test loop via robotics and automated metrology is identified as a key next step.
• Multimodal reasoning: To capture schematic, tabular, and mathematical forms of domain knowledge not explicit in natural language, planned extensions include multi-modal agent reasoning.

7. Impact and Future Directions

PhIDO demonstrates the feasibility of using AI agents—with modular task decomposition, schema-based validation, retrieval-augmented domain reasoning, and structured intermediate representations—for highly automated PIC design from natural language. As such, it lowers the barrier for PIC and photonics hardware design, and is positioned to underpin future self-driving photonics laboratories and intelligent foundry workflows. Anticipated developments include extended datasets and PDK support, standardized communication/model schemas, integrated robotic/experimental verification pipelines, and multi-agent systems leveraging multimodal domain knowledge for more reliable, scalable, and autonomous integrated photonics design (Sharma et al., 18 Aug 2025).