Design-Technology-Measurement Co-Optimization

• Design-Technology-Measurement Co-optimization is a cross-layer strategy that jointly optimizes design variables, technology choices, and measurement signals to enhance system performance.
• It integrates physical models, surrogate data, and validation metrics (e.g., SPICE, TCAD, and digital twins) into a unified multi-objective optimization framework.
• The approach leverages advanced techniques like GNNs and adaptive sensing to reduce simulation costs and improve reliability across semiconductors, robotics, and energy systems.

Design-Technology-Measurement Co-optimization is a cross-layer methodology in which design variables, technology or implementation choices, and measurement, validation, or uncertainty signals are optimized jointly rather than passed through a strictly one-way flow. In the cited literature, the term spans semiconductor DTCO and STCO, HW/SW co-design, adaptive sensing, robotics, digital twins for cooling infrastructure, and stochastic design-operation planning for energy systems. The shared structure is a closed loop that connects physical or technological models to system-level objectives and anchors the loop with SPICE, TCAD, silicon measurements, FPGA prototypes, digital twins, or operational telemetry (Censi, 2015, Ma et al., 2024, Jadhav et al., 15 May 2026).

1. Formal definition and mathematical basis

Andrea Censi’s "A Mathematical Theory of Co-Design" formalizes a design problem with implementation as the tuple

$(F,R,J,\mathrm{exec},\mathrm{eval}),$

where $F$ is the functionality space, $R$ the resources space, $J$ the implementation space, $\mathrm{exec}:J\to F$ maps implementations to provided functionality, and $\mathrm{eval}:J\to R$ maps them to required resources. For a requested functionality $f\in F$, the induced optimization problem is not generally a scalar minimization but an antichain of minimal, non-dominated resources: $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$ Co-design problems arise when such design problems are interconnected; monotone co-design problems (MCDPs) are the subclass for which functionality and resources are complete partial orders and the induced map is Scott continuous. The resulting least fixed point can be computed by Kleene iteration, and the class is closed under series, parallel, and feedback interconnection (Censi, 2015).

This formalism is unusually well aligned with design-technology-measurement couplings. The same source explicitly maps functionality to performance specifications, observability, estimation accuracy, validation confidence, test coverage, and latency; implementation to architecture, sensor type, compiler flags, calibration procedure, and test protocol; and resources to cost, power, energy, calibration time, measurement uncertainty, and test effort. In that sense, measurement is not external bookkeeping but part of the feasibility relation itself. A plausible implication is that design-technology-measurement co-optimization can be understood as a particular family of multi-objective co-design problems in which verification, calibration, or sensing burden is treated as a resource rather than an afterthought (Censi, 2015).

A second formal strand appears in adaptive sensing. "Adaptive Sensing beyond Non-Adaptive Information Limits" defines a sensor as the pair $(c,\pi)$, where $c$ is continuous hardware geometry and $F$0 is the adaptive measurement policy. Its joint dynamic programming formulation

$F$1

makes hardware geometry, policy, and inference part of a single optimization. The Bellman recursion is solved exactly at fixed $F$2, and the outer hardware gradient is obtained via a sharp Bellman maximum and the envelope theorem (Keshvari et al., 28 Apr 2026). This places measurement policy on the same footing as physical design.

2. Measurement and validation as active components of the loop

Across the literature, measurement appears in three distinct but related roles. First, it supplies training or calibration data. In "New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework", neural-network surrogate models are trained on TCAD simulations or silicon measurements and then inserted into HSPICE in place of, or alongside, a compact model when device physics is immature or compact-model derivation is slow (Zhang et al., 2019). In "Fast System Technology Co-Optimization Framework for Emerging Technology Based on Graph Neural Networks", a unified compact model connects device physics across CNT, IGZO, and LTPS, while GNNs accelerate both TCAD simulation and cell characterization (Ma et al., 2024).

Second, measurement can be replaced provisionally by validated virtual models. "An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models" shifts end-to-end performance estimation from the implementation phase to the concept phase through an abstract virtual system model composed of virtual hardware models plus a compiler-generated task graph. For a DilatedVGG system realized both as an AVSM and as FPGA hardware, the total inference-time deviation is $F$3, corresponding to up to $F$4 prediction accuracy; layer-wise deviations range from $F$5 to $F$6 (Klaiber et al., 2019). The same pattern appears in digital-twin work for infrastructure. "Co-Design Optimization for Data Center Cooling System via Digital Twin" validates a Modelica twin of the Frontier cooling plant against one year of telemetry using ASHRAE Guideline 14 metrics, reporting CV-RMSE between $F$7 and $F$8 and NMBE within $F$9, then derives a reduced-order surrogate whose baseline annual energy matches the twin within $R$0 (Jadhav et al., 15 May 2026).

Third, measurement enters as a fidelity or uncertainty constraint inside optimization. MORPH distinguishes Hw-Phy, a physics-based hardware model, from Hw-NN, a differentiable neural proxy, and optimizes policy and proxy jointly under a regularized divergence penalty

$R$1

The proxy is useful only insofar as it remains close to realistic hardware behavior, and the design extraction stage explicitly minimizes the mismatch between $R$2 and $R$3 (He et al., 2023). In MasCOR, by contrast, measurement and uncertainty are encoded through scenario generation and oracle trajectories: $R$4 scenario-design pairs are solved by LP to supervise an actor–critic operational policy, and the renewable generator is validated by discriminative scores below $R$5 for all four European sites (Kim et al., 3 Mar 2026).

These examples establish a common principle: measurement is not only a final benchmark. It can be the source of surrogate data, the calibration target of a digital twin, or an explicit constraint on model realism.

3. Semiconductor DTCO: from device physics to circuit figures of merit

Semiconductor DTCO provides the clearest examples of explicit design-technology-measurement linkage. The 2019 DTCO surrogate-model paper addresses the forward technology-to-design bottleneck that arises when a SPICE compact model is unavailable, inaccurate, or difficult to derive for emerging devices. For 16/14 nm FinFETs, training data are drawn from BSIM-CMG SPICE simulations over $R$6, $R$7, and $R$8 sweeps from $R$9 to $J$0 V in $J$1 mV steps; the resulting neural surrogate is validated on a $J$2k-sample test set and reports mean relative errors of about $J$3 for current and around $J$4–$J$5 for charge-related outputs. For TFETs, trained on TCAD data for a 2D n-type p-i-n structure with $J$6 swept from $J$7 to $J$8 V, the reported mean relative error is on the order of $J$9, and the model reproduces DC and transient circuit behavior, including the coupling-capacitance noise induced by large $\mathrm{exec}:J\to F$0 and unidirectional conduction in a 2-NAND TFET circuit (Zhang et al., 2019).

Variability-aware compact modeling extends the same loop to statistical performance estimation. "An Accurate Process Induced Variability Aware Compact Model-based Circuit Performance Estimation for Design-Technology Co-optimization" focuses on 7 nm FinFETs and the dominant process-induced variability sources LER and MGG. Using an experimentally validated BSIM-CMG baseline, the paper reports about $\mathrm{exec}:J\to F$1 accuracy improvement for NMOS and about $\mathrm{exec}:J\to F$2 for PMOS in DFoM estimation relative to the earlier state of the art. The improved variability model changes circuit conclusions: the framework yields a $\mathrm{exec}:J\to F$3 more optimistic estimate of $\mathrm{exec}:J\to F$4 under $\mathrm{exec}:J\to F$5 variation, supports about $\mathrm{exec}:J\to F$6 mV lower $\mathrm{exec}:J\to F$7 for the same worst-case SHM target, and implies dynamic and standby power reductions of about $\mathrm{exec}:J\to F$8 and $\mathrm{exec}:J\to F$9, respectively, at $\mathrm{eval}:J\to R$0 and $\mathrm{eval}:J\to R$1 V (Patil et al., 2021).

A related but earlier example is CNFET co-optimization. "Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations" jointly tunes CNT processing parameters $\mathrm{eval}:J\to R$2 and circuit-design choices such as minimum-width upsizing, selective upsizing, and aligned-active layouts. The framework is more than $\mathrm{eval}:J\to R$3 faster than prior detailed approaches and is designed to meet delay penalty $\mathrm{eval}:J\to R$4, $\mathrm{eval}:J\to R$5, $\mathrm{eval}:J\to R$6, and count-limited yield $\mathrm{eval}:J\to R$7 while preserving $\mathrm{eval}:J\to R$8 of projected EDP benefits. Its practical conclusion is that aggressively lowering $\mathrm{eval}:J\to R$9 is more effective than pushing $f\in F$0 much below about $f\in F$1 (Hills et al., 2015).

Monolithic 3D DRAM extends DTCO into routing, bonding, and system parasitics. "System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures" extracts device characteristics and array parasitics from TCAD, embeds them in SPICE, and evaluates alternative routing schemes under hybrid-bonding constraints. The optimized bitline selector-plus-strap design achieves $f\in F$2, corresponding to about $f\in F$3 density scaling over D1b 2D DRAM, with nominal $f\in F$4 ns versus $f\in F$5 ns in D1b and roughly a $f\in F$6 reduction in read/write energy. The paper explicitly attributes the viability of this point to the joint treatment of routing, selector technology, periphery access, and parasitic-aware sensing margin (Lee et al., 12 Mar 2026).

Taken together, these works show that semiconductor co-optimization is not limited to nominal PPA. It also includes variability statistics, routing parasitics, bias-region asymmetry, and the practical question of when compact-model fidelity is sufficient for downstream SRAM, inverter, or logic evaluation.

4. STCO and cross-hierarchy automation

At the cell-library and system-technology levels, the dominant issue is often turnaround time across large corner spaces. "Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks" models each standard cell as a directed graph with five node types $f\in F$7, a 3-layer GCN followed by 2 fully connected layers, and PVT-aware node features. Over $f\in F$8 training corners and $f\in F$9 unseen testing corners spanning over one million data points and $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$0 cell types, the model reports MAPE $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$1 for delay, power, and input pin capacitance, along with about $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$2 speedup over SPICE. At the system level, predicted libraries yield WNS absolute error $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$3 ps, leakage power percentage errors $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$4, and dynamic power percentage errors $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$5 on ten benchmarks (Ma et al., 2023).

The 2024 fast STCO framework generalizes this idea across the technology stack. It combines a GNN-based TCAD surrogate, a GNN-based cell-characterization model, and a unified compact model for CNT, IGZO, and LTPS. The technology-level tasks achieve over $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$6 acceleration, while the full STCO iteration flow achieves $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$7 to $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$8 speedup depending on the benchmark. The framework still relies on commercial tools for synthesis, placement, routing, DRC, and LVS, but compresses the technology-side bottlenecks enough to make repeated PPA-driven iteration practical (Ma et al., 2024).

Orthrus adds an explicit mechanism for transferring information between system and technology optimization. Its system loop uses Bayesian optimization with Expected Hypervolume Improvement and a Probabilistic Random Forest surrogate to explore the Pareto frontier of delay, power, and area; the inter-loop analysis then extracts per-cell delay and power contribution, subcircuit frequency, and a local Pareto-front normal direction to define the scalarized objective for the technology loop. The technology loop uses a neural-network-assisted enhanced differential evolution algorithm over process parameters such as phig_n, phig_p, hfin_nm, tfin_nm, lg_nm, lext_nm, lct_nm, plus multirow cell layouts and fused subcircuits. On 7 nm ASAP7, Orthrus reports $$h(f)=\operatorname{Min}\{\mathrm{eval}(i)\mid i\in J,\ f\le_F \mathrm{exec}(i)\}.$$9 hypervolume improvement over baseline, $(c,\pi)$0 delay reduction at iso-power, and $(c,\pi)$1 power savings at iso-delay (Ren et al., 16 Sep 2025).

Constraint-aware HW/SW co-design appears in photonic accelerator design as well. DxPTA formulates photonic transformer accelerator search around the simultaneous constraints

$(c,\pi)$2

and minimizes $(c,\pi)$3 over architectures parameterized by $(c,\pi)$4, $(c,\pi)$5, $(c,\pi)$6, $(c,\pi)$7, and $(c,\pi)$8. Guided by coherent optical dataflow and parameter-significance analysis, it achieves up to $(c,\pi)$9 area, $c$0 W power, $c$1 mJ energy, and $c$2 ms latency under budgets of $c$3, $c$4 W, $c$5 mJ, and $c$6 ms, with $c$7 faster search than exhaustive exploration (Putra et al., 2 Jun 2026).

A recurring theme in these STCO frameworks is that automation is structured rather than monolithic. System-level statistics, Pareto geometry, or workload constraints are distilled into smaller technology-side objectives, rather than pushing the full hierarchy into a single black-box optimizer.

5. Beyond semiconductors: sensing, robotics, infrastructure, and energy systems

The same co-optimization pattern recurs in domains where “technology” is not a transistor stack but an embodied physical system, an instrument geometry, or an infrastructure topology.

Domain	Coupled layers	Representative paper
Adaptive sensing	Geometry, policy, inference	(Keshvari et al., 28 Apr 2026)
DNN systems	Virtual hardware, compiler mapping, measurement	(Klaiber et al., 2019)
Robotics	Hardware design, control policy, hardware fidelity	(He et al., 2023)
Underwater docking	AUV geometry/control and dock entry/tolerance	(Wallen et al., 2021)
Data-center cooling	CDU partition, flow fractions, timestep controls	(Jadhav et al., 15 May 2026)
E-fuel systems	Plant sizing, renewable uncertainty, operation policy	(Kim et al., 3 Mar 2026)

In adaptive sensing, joint-DP shows that optimizing geometry with a non-adaptive information objective can be severely misleading. The radar beam-search example reports that classical information-bound-guided geometry selection loses $c$8 in attainable adaptive value; the superconducting-qubit flux sensor reduces deployed mean-squared error by $c$9 relative to a joint Bayesian Cramér–Rao baseline; and a $F$00-pixel photonic metasensor reduces deployed mean-squared error by $F$01 relative to a randomized baseline (Keshvari et al., 28 Apr 2026). The paper’s explicit claim is that for a sensor fabricated once but operated over its lifetime by an adaptive policy, joint optimization of hardware and policy is the minimum principled procedure.

Robotics papers in the set expose two different formulations. MORPH jointly learns control policy parameters $F$02 and a differentiable hardware proxy $F$03, then periodically searches for explicit hardware parameters $F$04 that make Hw-Phy match Hw-NN. The method was demonstrated on 2D reaching and 3D multi-fingered manipulation; the paper reports that task and hardware gradients have negative cosine similarity for about $F$05 of training steps in the mouse-clicking task, which motivates a PCGrad-style projection rule (He et al., 2023). By contrast, "A Co-Design Framework for High-Performance Jumping of a Five-Bar Monoped with Actuator Optimization" uses a two-stage pipeline: Stage 1 maps gear ratio to actuator mass, efficiency, and peak torque across SSPG, CPG, and WPG gearbox families; Stage 2 performs CMA-ES over morphology, motor selection, gear ratios, and virtual spring-damper control. The full co-design improves jump distance from $F$06 m to $F$07 m, about a $F$08 improvement, while reducing mechanical energy from $F$09 J to $F$10 J, a $F$11 reduction (Mishra et al., 7 Apr 2026).

In multidisciplinary marine design, "Co-design Optimization for Underwater Vehicle Docking Systems" formulates a nonlinear program over AUV frontal area $F$12, AUV length $F$13, control fidelity $F$14, relative dock entry area $F$15, and docking tolerance $F$16, with weighted objectives for hydrodynamic loss, cost, docking reliability, and versatility. Three weightings generate distinct optimized archetypes comparable to FlatFish, the MBARI 21-inch torpedo-form AUV, and ARTEMIS (Wallen et al., 2021). In the data-center cooling case, a three-layer optimization over the integer partition of $F$17 CDUs, continuous flow fractions, and per-timestep total flow and supply temperature evaluates all $F$18 feasible partitions across $F$19 timesteps. The global optimum is the two-subloop partition $F$20 with $F$21 annual cooling-energy savings, only $F$22 above Frontier’s existing three-subloop design at $F$23; optimized flow fractions reduce design sensitivity by $F$24 (Jadhav et al., 15 May 2026).

MasCOR shows the same logic under renewable uncertainty. The upper-level design vector $F$25 is optimized jointly with operational policy under stochastic renewable and grid-price scenarios. Renewable trajectories are generated by WGAN-GP plus an MMD-based discrepancy term, and a Decision Transformer-like actor–critic is trained on LP-optimal oracle trajectories. Relative to repeated LP solving, the learned agent evaluates $F$26 scenarios in $F$27 s versus $F$28 s for Gurobi, and $F$29 scenarios in $F$30 s versus $F$31 s; across diverse design settings, MasCOR reports lower optimality gaps and much smaller carbon-constraint violations than PPO, BC, DRL+BC, DT, or the ST baseline (Kim et al., 3 Mar 2026).

6. Recurring trade-offs, limitations, and common misconceptions

A recurrent misconception is that co-optimization is equivalent to a single end-to-end black-box search. Several papers explicitly reject that view. Orthrus argues that unified end-to-end search over architecture, logic synthesis, physical design, PDK, and cell layout is impractical because full VLSI flow evaluation can take hours to days and the search space is very high-dimensional (Ren et al., 16 Sep 2025). The Frontier cooling study likewise finds that once flow fractions are optimized, exact CDU-to-subloop assignment matters much less, which establishes a decision hierarchy rather than an undifferentiated search problem (Jadhav et al., 15 May 2026). This suggests that successful co-optimization often depends on decomposition plus information transfer, not on flattening all layers into one optimizer.

A second misconception is that surrogate models eliminate the need for physics or measurement. The DTCO surrogate-model paper explicitly states that the neural network is a surrogate model for the compact model and is not intended to explain the physics (Zhang et al., 2019). The AVSM paper makes a similar trade-off: virtual models are much faster than RTL or hardware prototypes, but the main source of deviation is the high-level memory-subsystem model, and the flow still requires later hardware validation (Klaiber et al., 2019). In fast STCO, the unified compact model remains the glue between device physics and GNN surrogates (Ma et al., 2024). Surrogates therefore replace repeated expensive evaluations, not the need for calibrated abstractions.

A third misconception is that non-adaptive information criteria are sufficient design objectives whenever measurement is involved. The sensing paper argues the opposite: mutual information, expected Fisher information, Bayesian CRB, or EVPI are diagnostics or surrogates, not definitive objectives, because the geometry maximizing such quantities can differ sharply from the geometry maximizing actual adaptive deployed value (Keshvari et al., 28 Apr 2026). The same article’s use of a sharp Bellman maximum rather than a softmax relaxation is specifically justified by the need to avoid biased outer gradients.

The main practical limitations are equally consistent across domains. Data generation cost is a central bottleneck: in TFET DTCO, more training data improve $F$32 but increase TCAD data-generation time (Zhang et al., 2019); the fast STCO framework relies on $F$33 independent devices for its TCAD surrogate and notes larger errors for flip and non-flip power because dynamic power spans several orders of magnitude across standard cells (Ma et al., 2024). Virtual-model and digital-twin flows still incur nontrivial preprocessing or build costs: in the AVSM case, about $F$34 of total runtime is spent in import/export and SystemC model build rather than graph generation itself (Klaiber et al., 2019). Some of the most consequential conclusions are also system-specific. In Frontier, the globally optimal topology is only marginally better than the existing hardware, so the paper recommends software-only flow-fraction optimization rather than plant reconfiguration (Jadhav et al., 15 May 2026).

The literature therefore supports a precise interpretation of Design-Technology-Measurement Co-optimization. It is neither simple hardware tuning nor generic end-to-end AI optimization. It is a structured, multi-objective methodology for propagating physical and technological choices upward to system behavior while propagating measurement, validation, and uncertainty information downward into design decisions.