Electronic-Photonic Integrated Circuits (EPICs)

• Electronic-Photonic Integrated Circuits (EPICs) are hybrid systems that merge photonics and electronics to enable ultra-high bandwidth, low latency, and scalable data movement.
• They employ diverse integration modalities—including monolithic, 3D-stacked, and chiplet-based architectures—to address performance and yield challenges.
• Design automation and closed-loop calibration in EPICs ensure precise device routing, robust photonic-electronic co-design, and improved system efficiency.

Electronic-Photonic Integrated Circuits (EPICs) are hybrid integrated systems in which photonic integrated circuits are combined with electronic control, memory, conversion, routing, and calibration circuitry so that optical and electrical functions are partitioned according to what each domain does best. In the recent literature, EPICs are treated not as a single device category but as a system class spanning interconnect fabrics, programmable photonic processors, coherent receivers, LiDAR engines, RF-photonic front ends, and large-scale physically aware design flows. Across these works, photonics is repeatedly used for ultra-high bandwidth, low latency, multiplexing, and analog linear transforms, while electronics supplies actuation, feedback, memory hierarchy, nonlinear processing, conversion, and orchestration (Ning et al., 2024, Chugh et al., 2022).

1. System rationale and defining characteristics

The contemporary rationale for EPICs is closely tied to the scaling trajectory of AI and high-performance computing. Several papers place the central pressure point at data movement rather than arithmetic alone: AI systems are moving toward multi-chiplet and wafer-level architectures, while electrical interconnects increasingly fail in bandwidth, latency, and scalability. Large-scale heterogeneous EPICs are therefore proposed as a response to the limits of purely electrical interconnects and computing units, especially where optical bandwidth and massive parallelism can be exploited at system scale (Zhou et al., 16 Apr 2026, Samanta et al., 4 Oct 2025).

A second defining feature is that EPICs are not purely optical computers. Recent reviews and system papers consistently assign photonics the fast linear and communication-heavy portions of the workload—matrix-vector multiplication, switching, broadcast, wavelength multiplexing, coherent mixing, or long-reach interconnect—while electronics remains responsible for memory, control, reconfiguration, conversion, and, when necessary, nonlinear processing. This division is explicit in photonic AI accelerator surveys, analog coherent-receiver demonstrations, and programmable photonic processor platforms (Ning et al., 2024, Zhu et al., 2 Apr 2025).

The literature also treats EPICs as a cross-layer problem rather than a component problem. Device geometry affects transmission, bandwidth, insertion loss, and yield; placement affects path length, congestion, crosstalk, and thermal feasibility; routing affects bend loss, crossings, and manufacturability; and post-fabrication correction determines whether the intended photonic response survives lithography and process variation. This cross-layer coupling is one reason recent EPIC work increasingly combines device synthesis, physical design, calibration, and post-layout evaluation in closed-loop workflows (Zhou et al., 16 Apr 2026).

2. Integration modalities and physical architectures

EPICs are implemented through multiple integration modalities. At the monolithic single-layer end, topology optimization has been used to devise an electronic-photonic circuit crossing that lets an optical waveguide and an electrical connection pass through one another in the same plane. That device reports up to $99.8\%$ optical transmission across an isolation trench while preserving electrical isolation, and it is used to realize a monolithic silicon nano-electro-mechanical add-drop switch in which photons, electrons, and mechanical motion coexist within the same layer (Lahijani et al., 2022). This result is significant because it addresses a routing bottleneck that had previously forced electrically controlled photonics toward multilayer metal architectures or topology restrictions.

A different monolithic architecture appears in thin-film lithium niobate RF-photonic front ends. A bow-tie antenna and a high-$Q$ microring modulator are co-designed and co-integrated on a $2 \times 1.7\,\mathrm{mm}^2$ chip, with RF resonance and optical resonance both set to $30.5\,\mathrm{GHz}$. The device reports $Q \approx 4.4 \times 10^5$, a first-order sideband enhancement of $15.2\,\mathrm{dB}$, and a figure of merit of $3.88\,\mathrm{W}^{-1/2}$, and it is then used for centimeter-level radar ranging accuracy and up to $3.2\,\mathrm{Gbps}$ wireless communication capacity (Liu et al., 10 Nov 2025). Here, EPIC means direct RF-to-optical conversion in a monolithic wireless frontend rather than only optical computing or interconnect.

Back-end-of-line monolithic integration provides yet another architecture. Piezo-optomechanical photonic integrated circuits have been fabricated directly on completed commercial CMOS driver wafers on $200\,\mathrm{mm}$ wafers, using a $180\,\mathrm{nm}$ CMOS digital backplane with a $Q$0 electrode array, more than $Q$1 million independently addressable electrodes per die, and $Q$2 electrode pitch. In this platform, segmented photonic devices function as Photonic Digital-to-Analog Converters (PDACs), translating low-voltage digital backplane outputs into multi-bit optical phase, amplitude, and resonance control for Mach–Zehnder interferometers, switching trees, and tunable rings (Zimmermann et al., 1 Jul 2026). This architecture is especially relevant to dense programmable photonics because it shifts the control bottleneck into a wafer-scale electronic backplane.

Three-dimensional heterogeneous integration extends EPICs beyond monolithic stacks. In mixed-precision photonic computing, the photonic integrated circuit and electronic integrated circuit are 3D integrated through Direct Bond Interconnect, with a photonic compute plane based on PCM-AlGaAs mem-resonators and a CMOS control plane containing DACs, ADCs, TIAs, calibration, and pulse circuitry. The claimed targets include precision greater than $Q$3 bits, scalability greater than $Q$4, and power efficiency less than $Q$5 (Charalampous et al., 5 Aug 2025). In HPC interconnects, a 3D chiplet-stacking EPIC platform uses Through Silicon Optical Vias (TSOVs) for vertical optical data transfer while retaining electrical TSVs and 2.5D electrical links for power delivery and short-reach communication; the platform is benchmarked at $Q$6 bandwidth density with a pathway to $Q$7 (Samanta et al., 4 Oct 2025).

Packaging-level heterogeneity is represented by 3D-nanoprinted interposers. A printable interposer combining chip-coupling frames, fiber-guiding funnels, and off-chip parabolic micro-reflectors has been used to connect photonic chiplets from different material platforms without modifying the native process flow of either die. The reported results include a $Q$8 mode-field-dimension conversion ratio, $Q$9 excess loss on top of $2 \times 1.7\,\mathrm{mm}^2$0 inherent coupling loss for fiber-to-chip coupling, and $2 \times 1.7\,\mathrm{mm}^2$1 die-to-die coupling loss between silicon and InP chips across $2 \times 1.7\,\mathrm{mm}^2$2–$2 \times 1.7\,\mathrm{mm}^2$3 (Huang et al., 2024). The significance lies in treating optical chiplets as modular elements in a heterogeneous system rather than forcing all EPIC functions onto one substrate.

3. Design automation, placement-routing, and cross-layer simulation

Large EPICs have made manual photonic design increasingly untenable. Recent physical design papers explicitly describe conventional flows as fragmented: device synthesis, placement, routing, layout export, and post-layout or post-fabrication validation are often separate and manual, which is especially problematic for inverse-designed devices with fabrication-sensitive subwavelength geometries (Zhou et al., 16 Apr 2026). As a result, contemporary EPIC research increasingly treats design automation as a first-class systems problem.

An end-to-end example is OptoSynthesizer, a unified flow from EPIC netlists to fabrication-ready GDS layouts. It combines three major stages: fabrication-robust inverse design and photonics-aware inverse lithography, GPU-accelerated routing-informed placement, and hierarchical curvy-aware waveguide routing with global-planning-assisted electrical-optical co-routing. The flow is positioned as a closed-loop Device-Technology-System Co-Optimization framework and is integrated with GDSFactory for layout and post-layout netlist export (Zhou et al., 16 Apr 2026). The fabrication side is especially notable: under $2 \times 1.7\,\mathrm{mm}^2$4 DUV lithography, several inverse-designed devices reportedly have near-zero yield without inverse lithography, whereas PRISM-based photonics-aware inverse lithography raises yield to around $2 \times 1.7\,\mathrm{mm}^2$5, including $2 \times 1.7\,\mathrm{mm}^2$6 to $2 \times 1.7\,\mathrm{mm}^2$7 for a bending device and $2 \times 1.7\,\mathrm{mm}^2$8 to $2 \times 1.7\,\mathrm{mm}^2$9 for a crossing. On the layout side, Apollo places PICs with over $30.5\,\mathrm{GHz}$0 components in about $30.5\,\mathrm{GHz}$1 seconds, LiDAR 2.0 routes more than $30.5\,\mathrm{GHz}$2 nets in $30.5\,\mathrm{GHz}$3 seconds, and LiDAR 3.0 reports a $30.5\,\mathrm{GHz}$4 speedup for electrical routing (Zhou et al., 16 Apr 2026).

PoLaRIS addresses a similar EPDA problem with a different emphasis. Its device-level subsystem combines BOSON, described as a fabrication-aware stochastic subspace inverse-design optimizer, with MAPS, an AI-augmented infrastructure for data generation, training, and inverse design. Its physical-layout subsystem again uses Apollo and LiDAR to generate DRV-free layouts for large-scale PIC and EPIC systems (Zhou et al., 30 Jul 2025). The framework is motivated by the fact that modern PICs now integrate hundreds to thousands of components and that standard electronic placement and routing abstractions transfer poorly to single-layer, orientation-sensitive, bend-constrained photonic routing.

Cross-layer system simulation is handled by SimPhony, which provides a netlist-based representation for heterogeneous EPIC architectures, optics-specific dataflow modeling with wavelength, polarization, mode, spatial, and temporal parallelism, data-aware energy estimation, layout-aware area estimation, bandwidth-adaptive memory modeling, and link-budget analysis (Yin et al., 2024). A technically important point is that SimPhony uses directed 2-pin nets to model unidirectional optical signal flow, derives weighted DAGs from node-level topology, and shows that layout-unaware methods can underestimate node area by $30.5\,\mathrm{GHz}$5. This is significant because it links architecture-level comparisons to physical realizability rather than to abstract compute arrays alone.

4. Electronic control, calibration, and internal observability

A recurring theme in EPIC research is that programmable photonics is inseparable from electronic feedback. Reconfigurable photonic circuits need working-point stabilization, drift compensation, and scalable channel-wise actuation, and board-level control is repeatedly described as too bulky and power-hungry for large photonic systems. One response is an integrated multi-channel CMOS ASIC controller fabricated in AMS $30.5\,\mathrm{GHz}$6 technology, with an $30.5\,\mathrm{GHz}$7-channel chip used pairwise to control a $30.5\,\mathrm{GHz}$8-channel silicon-photonics adaptive beam coupler. Each channel includes a TIA, a gated integrator, a $30.5\,\mathrm{GHz}$9-bit ADC sampled at $Q \approx 4.4 \times 10^5$0, digital dither extraction and integral feedback, and a pair of $Q \approx 4.4 \times 10^5$1-bit DACs with high-current heater drivers. The chip has active area about $Q \approx 4.4 \times 10^5$2, dissipates about $Q \approx 4.4 \times 10^5$3 per channel, converges a full $Q \approx 4.4 \times 10^5$4-stage $Q \approx 4.4 \times 10^5$5 mesh in about $Q \approx 4.4 \times 10^5$6, supports an effective tracking bandwidth of about $Q \approx 4.4 \times 10^5$7, and is used for successful transmission of a $Q \approx 4.4 \times 10^5$8 PAM-4 signal through an optical free-space link (Sacchi et al., 16 Jan 2025).

Closed-loop electronic-photonic control also appears in coherent communication. A silicon photonic integrated coherent receiver fabricated in a $Q \approx 4.4 \times 10^5$9 SOI platform is integrated with a SiGe carrier phase recovery EIC in ST $15.2\,\mathrm{dB}$0 BiCMOS. The PIC performs $15.2\,\mathrm{dB}$1 optical hybrid mixing, balanced detection, and phase shifting in the LO arm; the EIC extracts phase error and feeds back to the phase shifter. In the homodyne/self-homodyne case, the loop is described by $15.2\,\mathrm{dB}$2 for $15.2\,\mathrm{dB}$3, with the corrective phase $15.2\,\mathrm{dB}$4, and the system is demonstrated on a $15.2\,\mathrm{dB}$5 QPSK homodyne link over $15.2\,\mathrm{dB}$6 single-mode fiber (Chugh et al., 2022). This architecture makes explicit that EPICs often place optical front-end computation and electrical feedback in the same functional loop.

Internal observability is another control prerequisite. A universal nondestructive method has been proposed for recovering component-level loss and gain inside PICs by using nonlinear optical elements as optical power discriminators. For facet-loss extraction, the paper gives

$15.2\,\mathrm{dB}$7

where $15.2\,\mathrm{dB}$8 is total fiber-to-fiber loss and $15.2\,\mathrm{dB}$9 is the directional threshold difference. The reported precision is better than $3.88\,\mathrm{W}^{-1/2}$0, and the method measures a waveguide-crossing loss of $3.88\,\mathrm{W}^{-1/2}$1, consistent with a foundry value of $3.88\,\mathrm{W}^{-1/2}$2 (Chen et al., 21 Oct 2025). For EPICs, this kind of “see-inside” metrology is valuable because end-to-end insertion loss alone is rarely sufficient for debugging dense heterogeneous circuits.

The post-fabrication literature also corrects a common misconception: lithography correction is not equivalent to full system closure. In a Clements$3.88\,\mathrm{W}^{-1/2}$3 coherent interferometer array, post-fabrication total intensity degrades from schematic $3.88\,\mathrm{W}^{-1/2}$4 to $3.88\,\mathrm{W}^{-1/2}$5, recovers to $3.88\,\mathrm{W}^{-1/2}$6 with inverse lithography, but distribution correctness requires phase matching or calibration; the distribution deviation NMSE drops from $3.88\,\mathrm{W}^{-1/2}$7 with ILT alone to $3.88\,\mathrm{W}^{-1/2}$8 with ILT plus phase matching (Zhou et al., 16 Apr 2026). The implication is direct: yield-aware geometry correction and run-time calibration solve different EPIC problems and are not interchangeable.

5. Computing, interconnect, communication, and sensing

EPIC application domains now extend well beyond simple optical links. In photonic computing, one direction emphasizes programmable or reconfigurable photonic processors. A versatile silicon photonic processor for AI clusters uses a $3.88\,\mathrm{W}^{-1/2}$9 square recirculating MZI mesh with $3.2\,\mathrm{Gbps}$0 programmable unit cells and over $3.2\,\mathrm{Gbps}$1 components on a $3.2\,\mathrm{Gbps}$2 SOI chip. With an electronic control module and a Testing, Compilation, Adjustment framework, the processor implements $3.2\,\mathrm{Gbps}$3 dual-direction unitary matrix multiplication, $3.2\,\mathrm{Gbps}$4 non-unitary multiplication, image-recognition networks, wavelength locking, $3.2\,\mathrm{Gbps}$5 channel switching, and photonic physical unclonable functions. For matrix-vector computing it reports $3.2\,\mathrm{Gbps}$6, $3.2\,\mathrm{Gbps}$7, and $3.2\,\mathrm{Gbps}$8 correlation between measured and theoretical results (Zhu et al., 2 Apr 2025). Another direction uses more speculative 3D compute stacks: mixed-precision photonic in-memory computing based on PCM-AlGaAs mem-resonators and CMOS control targets greater than $3.2\,\mathrm{Gbps}$9-bit precision, greater than $200\,\mathrm{mm}$0 scalability, and greater than $200\,\mathrm{mm}$1 million operations across wavelength, spatial, and temporal domains (Charalampous et al., 5 Aug 2025).

Analog physics-based computing is another EPIC application class. A reconfigurable application-specific photonic integrated circuit solves heat-diffusion PDEs on a $200\,\mathrm{mm}$2 nanophotonic beam-mesh network using electro-optically switched GSSe attenuators. The active version reports $200\,\mathrm{mm}$3 accuracy on the main heat-diffusion problem and optical solution latency in the hundreds of nanoseconds, contrasted with several milliseconds for a COMSOL numerical solve (Shen et al., 2022). At a more architectural extreme, 3D EPICs have been proposed as substrates for brain-derived neuromorphic systems combining photonic long-range communication, electronic local processing, and ionic or memristive dynamicity across stacked planes connected by TSOVs and TSVs (Yoo et al., 2024).

Interconnect-centric EPICs focus on bandwidth density and energy per bit. The 3D chiplet-stacking optical-interconnect platform mentioned earlier is benchmarked at $200\,\mathrm{mm}$4 bandwidth density and proposes a path to $200\,\mathrm{mm}$5 by combining TSOVs, WDM scaling, process contraction, and monolithic photodetector/TIA integration (Samanta et al., 4 Oct 2025). These system-level interconnect papers are conceptually aligned with survey arguments that photonic-electronic accelerators are attractive because optical broadcast, wavelength multiplexing, and low-latency propagation can relieve the most severe bandwidth and interconnect bottlenecks of AI and HPC workloads (Ning et al., 2024).

Communication and sensing EPICs are equally diverse. A coherent LiDAR engine integrates a $200\,\mathrm{mm}$6 SiGe BiCMOS high-voltage arbitrary waveform generator, a hybrid Vernier laser with PZT tuning, and an erbium-doped waveguide amplifier, reporting $200\,\mathrm{mm}$7 optical chirp excursion, $200\,\mathrm{mm}$8 sweep rate, $200\,\mathrm{mm}$9 optical output power, $180\,\mathrm{nm}$0 ranging, $180\,\mathrm{nm}$1 most probable range resolution, $180\,\mathrm{nm}$2 precision, and chirp nonlinearity below $180\,\mathrm{nm}$3 (Lukashchuk et al., 2023). In monolithic RF photonics, the thin-film lithium-niobate receiver demonstrates integrated sensing and communication and real-time HD video transmission under motion (Liu et al., 10 Nov 2025). In adaptive free-space photonics, the ASIC-controlled beam coupler shows automatic coupling of arbitrary beams into a single-mode waveguide and dynamic compensation of turbulence-induced distortions (Sacchi et al., 16 Jan 2025). These papers collectively show that EPICs now encompass not just on-chip optical processing but complete optoelectronic front ends.

6. Limits, misconceptions, and prospective directions

A persistent misconception is that photonics alone determines EPIC efficiency. In practice, surveys of photonic-electronic AI hardware emphasize that conversion and data movement dominate system energy: the electrical-optical and optical-electrical interfaces, together with memory traffic, can account for more than $180\,\mathrm{nm}$4 of total energy in some accelerator decompositions (Ning et al., 2024). This is one reason recent EPIC work devotes as much effort to controllers, calibration loops, placement-routing, and memory-aware architecture as to photonic core devices.

Another misconception is that there is a single preferred integration path. The current literature contains monolithic single-layer devices, BEOL monolithic photonics on CMOS backplanes, DBI-bonded 3D stacks, chiplet-stacking platforms with TSOVs, and printable interposers for heterogeneous chiplets (Lahijani et al., 2022, Zimmermann et al., 1 Jul 2026, Samanta et al., 4 Oct 2025, Huang et al., 2024). This diversity reflects application dependence rather than immaturity alone: cryogenic piezo-optomechanics, RF front ends, AI tensor cores, and coherent interconnects impose different requirements on loss, pitch, voltage, thermal budget, and materials.

The technical bottlenecks are correspondingly broad. Physical-design papers note that exact phase matching through routing alone is extremely difficult in dense layouts, that specialized process and digital-twin models are required for fabrication-aware optimization, and that current flows do not provide a universal solution for every EPIC technology stack or packaging scenario (Zhou et al., 16 Apr 2026). EPDA papers identify open challenges in differentiable photonic simulation, multi-layer and 3D routing, better yield and variability models, and true photonic-electronic co-design beyond photonic-only layout legality (Zhou et al., 30 Jul 2025). Brain-derived 3D EPIC proposals add a further layer of uncertainty by explicitly acknowledging integration complexity, device variability, and the gap between promising components and large-scale self-learning systems (Yoo et al., 2024).

Prospective directions increasingly include sustainability as well as performance. A recent perspective argues that EPICs can lower both operational and embodied carbon footprint because active PICs often require only two metal layers, whereas modern digital EICs may use $180\,\mathrm{nm}$5 metal layers, and because photonic devices can be fabricated in relaxed process nodes with fewer defects (Yin et al., 9 Sep 2025). The paper formalizes total carbon footprint as

$180\,\mathrm{nm}$6

and connects long-term sustainability to compact EPDA, reconfigurability, and robustness. This suggests that future EPIC evaluation is likely to treat yield, calibration burden, service lifetime, and carbon-normalized performance as co-equal metrics with bandwidth, loss, and TOPS/W.