SimPhony: Heterogeneous EPIC AI Simulation

• SimPhony is a cross-layer simulation framework that models heterogeneous EPIC AI systems by integrating photonic device physics with architecture-level performance metrics.
• It represents photonic circuits as weighted directed acyclic graphs, enabling detailed analysis of dataflow, energy consumption, area, and optical link budgets.
• It interfaces with machine learning platforms to inject device-level noise and perform hardware-aware optimization for end-to-end AI workload co-simulation.

SimPhony is a cross-layer modeling and simulation framework for heterogeneous electronic-photonic integrated circuit (EPIC) AI systems, providing unified evaluation from device-level physics and compact models through to architecture, dataflow, system performance, and AI application co-simulation. The framework targets next-generation AI hardware that integrates photonic tensor core architectures with electronic logic and memory, enabling system designers and researchers to rigorously explore the design space of photonic accelerators using high-fidelity, layout-aware, and data-driven metrics. SimPhony is open source, Python-based, and supports seamless integration with machine learning training platforms, thus enabling co-design and hardware-aware optimization workflows across disciplines (Yin et al., 2024, Yin et al., 31 Dec 2025, Zhou et al., 31 Dec 2025).

1. Motivation, Scope, and Distinctive Features

SimPhony addresses critical challenges in modeling EPIC AI systems, including the diversity of photonic tensor core designs (microring resonator arrays, Mach–Zehnder meshes, crossbars), unique optics-specific parallelism (spatial, spectral, modal, polarization dimensions), and the necessity of accurate device–circuit–layout co-modeling. Unlike conventional digital or electronic hardware simulators, SimPhony is architected to:

• Represent arbitrary, possibly heterogeneous, photonic circuit topologies as weighted directed acyclic graphs, capturing divergent waveguide interconnections, device scaling rules, and spatial layout constraints.
• Model dataflows natively exploiting spectral (wavelength-division multiplexing), analog accumulation, and temporal reuse, features intrinsic to photonic computation but absent in electronic-only architectures.
• Estimate energy, area, and bandwidth at a data-aware level, incorporating operand bitwidths, sparsity masks, device operating points, and physically realistic link budgets.
• Integrate AI workload simulation with hardware non-idealities, including phase noise, quantization, and drift, through extensions such as TorchONN.
• Provide open-source accessibility and extensibility to enable rapid iteration, hardware/software co-design, and democratization of photonic accelerator research (Yin et al., 2024, Zhou et al., 31 Dec 2025).

2. Modeling Architecture and Workflow

The SimPhony framework comprises four logical modules that map physical device models to architectural performance:

1. Device Library (SimPhony-DevLib): Encapsulates parameterized models for photonic (MZI, MRR, phase shifter), electrical (DAC, ADC), and memory devices. Each device instance is defined by its footprint, static/dynamic power, insertion loss, bandwidth, and tuning parameters, typically derived from numerical simulations or foundry data.

2. Architecture Builder (SimPhony-Arch): Defines and instantiates the photonic tensor core topology as a hierarchical, parametric netlist. The circuit is modeled as a directed graph with nodes (device instances) and weighted edges (insertion loss per connection), leveraging user-specified scaling rules to enable flexible, multi-core layouts.

3. Simulator (SimPhony-Sim): Executes dataflow analysis, memory bandwidth adaptation, performance (throughput, latency) evaluation, data-aware energy estimation, and layout-aware area calculation. The simulation engine extracts workloads from AI models, models multi-dimensional photonic parallelism, and applies link budget averaging over the full netlist topology.

4. Training Framework Interface (TorchONN): Seamlessly connects to machine learning frameworks. During training and inference, it injects modeled device/circuit noise and quantization into neural network execution, supports hardware-in-the-loop learning, and exports workloads for end-to-end system co-simulation (Yin et al., 2024).

The typical workflow progresses from device and topology specification (via YAML or direct Python API) to AI model conversion, workload export, architecture simulation, and iterative design space exploration.

3. Fundamental Modeling Methodologies

Photonic circuits modeled in SimPhony use a block-based abstraction where each component is represented by compact models. Core methodologies include:

• Directed 2-pin Netlists: EPIC circuits are abstracted as G=(V,E), with V as device instances and E as waveguide connections carrying insertion loss as edge weights. Netlist expansion handles multi-tile, multi-core scaling and device sharing.
• Dataflow Analysis: SimPhony extracts tensor dimensions and photonic core properties from mapped AI workloads, supporting analytic blocking loops and photonic-specific parallelism. Throughput is computed as $T_{op}=R_\lambda \cdot N_{core} \cdot f$, where $R_\lambda$ is wavelength parallelism, $N_{core}$ number of cores, and $f$ modulator clock.
• Energy and Area Estimation: Device- and data-aware power is modeled, e.g., $E_{MZM} = \int_0^T P_{MZM}(x(t)) dt$, and layout-aware area estimation utilizes floorplanning heuristics to respect minimal device spacing, bend radius, and bus pitch. Link budgets are solved along weighted DAG paths to yield insertion loss and required optical power (Yin et al., 2024, Yin et al., 31 Dec 2025).
• Hardware-aware Learning: By integrating with TorchONN, SimPhony allows noise, quantization, and thermal drift to be injected as differentiable perturbations into PyTorch models, enabling co-optimization of AI algorithms and hardware characteristics (Yin et al., 2024).

4. Quantitative Modeling and System Metrics

Physical layer parameters are systematically translated into system-level performance using physics-derived compact models and analytic equations. Key quantities include:

• Insertion Loss: For a path of length $L$ and loss coefficient $\alpha$, $IL(L) = 10^{-\alpha L / 10}$.
• DAC/ADC Energy: For resolution $N$ and sampling rate $f_s$, $P_{DAC} = C_{DAC} V_{max}^2 f_s 2^N$, $P_{ADC} = C_{ADC} V_{max}^2 f_s 2^N$.
• Throughput: For $N_{WDM}$ channels at $f_{mod}$, throughput is $N_{WDM} \cdot f_{mod}$.
• Energy per MAC: Sum over optical/electrical energies: $$E_{MAC}=E_{laser}+E_{mod}+E_{waveguide}+E_{det}+E_{ADC}+E_{DAC}$$.
• Latency: $T_{opt} = L_{path}/v_g + T_{DAC} + T_{ADC}$, where $v_g$ is group velocity.
• Link Budget: Minimum laser output, power at the detector, and SNR are modeled explicitly, with attention to photodetector sensitivity and extinction ratios.

Representative results show, for example, 1.6 TeraMAC/s throughput and ~15 pJ/MAC energy per operation for BERT-style self-attention with modern photonic tensor core parameters and 64 WDM channels. As integration density increases, insertion loss and crosstalk degrade SNR, and SimPhony projects system accuracy under these effects, guiding retraining or architecture modifications as needed (Yin et al., 31 Dec 2025, Zhou et al., 31 Dec 2025).

5. Design Space Exploration, Validation, and Use Cases

SimPhony supports systematic design-space exploration via API-driven or configuration-sweep workflows. Optimization routines can perform global (e.g., genetic, Bayesian) or local (adjoint, gradient) search, constrained by throughput, energy, SNR, area, and thermal budgets.

Validation studies demonstrate high modeling fidelity, with area and energy metrics within 5–10% of published chip measurements for TeMPO and Lightening-Transformer architectures. Use cases include:

• Multi-wavelength parallelism scaling (latency decreases as $1/R_\lambda$; laser/MZM energy increases $\propto R_\lambda$).
• Bit-precision sweeps for DAC/ADC trade-offs (energy scales as $2^{N_{bits}}$).
• Floorplan calibration (row-based area estimate matches real layouts within 5%).
• Mixed architecture mapping for VGG-8, exploring heterogeneous photonic core integration.
• Robustness and power optimization for sparse photonic accelerators (e.g., SCATTER).

These case studies confirm SimPhony’s ability to span from device-physics to end-to-end AI application metrics (Yin et al., 2024, Zhou et al., 31 Dec 2025).

6. Implementation, Extensibility, and Limitations

SimPhony is implemented in Python, supporting modular YAML/JSON configuration and custom device/architecture extension. The toolkit includes:

• Device parameterization files for new photonic/electronic models.
• User-specified topology expansion via symbolic scaling rules.
• Layout-aware netlist generation and area/energy modeling.
• Hooks for external optimizer integration, enabling automated design space exploration.

Limitations include surrogate model degradation outside trained parameter regimes, lack of internal layout placement/routing (assumes pre-placed components), and idealized electronic backends. Scalability is contingent on surrogate training set size and GPU memory for large inverse-design loops. Envisioned future directions are push-button arch-to-layout automation, tight foundry PDK coupling, and expanded architecture and layout tool support (Yin et al., 2024, Zhou et al., 31 Dec 2025).

7. Impact and Research Significance

SimPhony provides a coherent, extensible platform that bridges device physics, circuit design, system architecture, and AI training/inference for EPIC AI hardware exploration and evaluation. It enables multi-domain research collaboration and rapid iteration that would otherwise be bottlenecked by slow, ad hoc, or discipline-specific tools. The explicit capture of photonic-specific parallelism, loss, and dataflow challenges is essential for the practical realization and robust scaling of photonic AI accelerators. Its adoption in multiple research groups and benchmarking studies reflects its status as a reference-grade tool in the emerging field of hybrid electronic-photonic computing (Yin et al., 2024, Yin et al., 31 Dec 2025, Zhou et al., 31 Dec 2025).