MoS₂ Charge-Trap Memory Fundamentals
- MoS₂ charge-trap memory is a nonvolatile technology where MoS₂ FETs store data by inducing electrostatic shifts in the channel’s threshold voltage through engineered dielectric stacks.
- Device architectures vary from dual-gate designs with Al₂O₃/HfO₂/Al₂O₃ stacks to fully 2D floating-gate configurations, each offering distinct charge storage and switching properties.
- Electrical benchmarks demonstrate high on/off ratios, dynamic threshold shifts, and endurance characteristics that underline both the potential and challenges in optimizing charge-trap memory performance.
Searching arXiv for recent and foundational papers on MoS charge-trap memory and adjacent mechanisms. arXiv search: "MoS2 charge trap memory HfO2 Al2O3" MoS charge-trap memory is a class of nonvolatile memory in which a MoS field-effect transistor functions as the readout element while information is stored as charge in a nearby storage medium that electrostatically shifts the threshold voltage or channel conductance. In the arXiv literature, the most direct embodiments are a few-layer dual-gate MoS memory using an AlO/HfO/AlO charge-trap stack and an all-2D monolayer MoS/graphene floating-gate memory, while a broader surrounding literature examines interface traps, oxide traps, photodoping, ionic motion, and memristive defect dynamics that can produce memory-like states in MoS0 devices (Zhang et al., 2014, Bertolazzi et al., 2013).
1. Canonical forms and scope
Within the strictest usage, MoS1 charge-trap memory refers to transistor memories in which stored charge is written electrically and read through a persistent threshold-voltage or current shift of a MoS2 channel. Two device lineages dominate the early arXiv record. One is a few-layer MoS3 top-gated memory transistor with a conventional high-4 Al5O6/HfO7/Al8O9 stack, where HfO0 is the trap medium and the back gate tunes the apparent memory response (Zhang et al., 2014). The other is a fully 2D nonvolatile cell in which monolayer MoS1 is the semiconducting channel, graphene forms the source and drain contacts, and multilayer graphene serves as the floating charge-storage layer above a HfO2 tunnel dielectric (Bertolazzi et al., 2013).
The first architecture is a conventional charge-trap memory in the SONOS-like sense: the storage function resides in a trap-rich dielectric, the program and erase operations are field-driven, and the memory window is a threshold shift in a MoS3 FET. The second is a floating-gate memory rather than a distributed trap-layer memory, but it belongs to the same broader charge-storage family because information is stored as isolated charge and read electrostatically through the MoS4 transistor (Bertolazzi et al., 2013).
A larger body of MoS5 memory literature falls outside this narrow definition. Persistent photoconductivity devices, photodoping memories, irradiation-induced oxide-trap memories, thermally activated ion-modulated memtransistors, and grain-boundary memristors all generate nonvolatile or long-lived states in MoS6, but they do not all use a dedicated tunnel-dielectric/trap-layer/blocking-dielectric stack. That distinction is essential because identical observables—hysteresis, threshold shift, or multilevel conductance states—can arise from different physical reservoirs of stored state.
2. Device architectures and materials stacks
The dual-gate few-layer MoS7 charge-trap memory uses a degenerately doped Si substrate as the back gate, 8 nm SiO9 as the back-gate dielectric, a few-layer MoS0 flake identified as approximately 1–2 layers, Cr/Au source and drain contacts of 3 nm, and a local top-gate stack of 4 nm Al5O6/HfO7/Al8O9, followed by a Cr/Au top-gate electrode of 0 nm (Zhang et al., 2014). In this stack, the 1 nm Al2O3 is the tunneling layer, the 4 nm HfO5 is the charge-trap layer, and the 6 nm Al7O8 is the blocking layer. The device is explicitly dual-gated: the top gate programs and erases the HfO9 storage medium, while the Si back gate tunes channel electrostatics and therefore the measured memory window and current ratio (Zhang et al., 2014).
The all-2D floating-gate memory is built on heavily doped 0-Si with 1 nm thermal SiO2. Patterned CVD graphene stripes about 3m wide and spaced by 4m act as source and drain electrodes. A monolayer MoS5 flake bridges adjacent graphene stripes and forms the transistor channel. Above the channel lies a tunnel stack described as approximately 6 nm Al7O8 plus 9 nm HfO0, then a multilayer graphene floating gate about 1 nm thick, corresponding to roughly 2–3 graphene layers, then a blocking stack of about 4 nm Al5O6 plus 7 nm HfO8, and finally a Cr/Au top control gate (Bertolazzi et al., 2013). This architecture is “fully 2D” in the sense that the active semiconductor channel, the lateral contacts, and the floating gate are all graphitic or layered van der Waals materials.
A later comparative study on few-layer black phosphorus is frequently relevant to MoS9 because it isolates the transferable value of the Al0O1/HfO2/Al3O4 concept. That device used a 5 nm Al6O7/HfO8/Al9O0 stack deposited by ALD at 1C, with the 2 nm Al3O4 as tunnel oxide, 5 nm HfO6 as trap layer, and 7 nm Al8O9 as blocking oxide; the study explicitly argued that the stack design, tunneling mechanism, retention methodology, and trapped-charge estimation were directly transferable to MoS0 memory design (Feng et al., 2015).
3. Storage physics and program/erase mechanisms
In the few-layer MoS1 Al2O3/HfO4/Al5O6 memory, the dominant mechanism is field-driven tunneling between the MoS7 channel and the HfO8 storage layer through the 9 nm Al00O01 tunnel oxide. Positive top-gate bias causes electrons in the MoS02 channel to tunnel through the tunnel oxide into HfO03 via Fowler–Nordheim tunneling, producing a positive threshold shift and the programmed state. Negative top-gate bias drives previously trapped electrons back and also enables holes to tunnel into HfO04, producing a negative threshold shift. The large memory window therefore reflects bidirectional storage: electron trapping on one side of the hysteresis and hole trapping on the other (Zhang et al., 2014).
That work estimates stored charge density from threshold shift using
05
where 06 is the capacitance between the HfO07 trap layer and the top gate through the blocking Al08O09, 10, and 11 nm (Zhang et al., 2014). The dynamic trapping rate is extracted from
12
This methodology became a template for subsequent MoS13 charge-storage analysis because it links a directly measured transfer-curve shift to an areal charge density and to pulse-width-dependent injection kinetics (Zhang et al., 2014).
In the all-2D floating-gate device, positive control-gate bias accumulates electrons in the 14-type monolayer MoS15 channel and lowers the tunnel barrier sufficiently for electrons to tunnel through HfO16 into the multilayer graphene floating gate. Negative control-gate bias discharges the floating gate by driving electrons back to the MoS17 channel. The state is read as a threshold shift in 18, and the stored electron density is estimated by
19
Using this framework, the work interpreted the storage node as a deep graphene-related potential well, with a MoS20-to-HfO21 barrier magnitude of about 22 eV and a floating-gate electron well depth magnitude of about 23 eV (Bertolazzi et al., 2013).
These two mechanisms are related but not identical. In the HfO24 trap-layer device, storage is distributed across trap states in a dielectric. In the graphene floating-gate device, storage occurs on an isolated conductive node with a high density of states. Both convert stored charge into a threshold-voltage shift of a MoS25 transistor, but their retention limits, scaling rules, and sensitivity to interface parasitics differ.
4. Electrical characteristics and benchmarking
The few-layer dual-gate HfO26-trap memory established the principal benchmark for conventional MoS27 charge-trap memory on arXiv. Its top-gated transfer curves showed a maximum on/off ratio higher than 28 and a field-effect mobility of approximately 29. A top-gate sweep from 30 V to 31 V and back at 32 yielded a memory window of about 33 V. The back gate tuned this window from 34 V at 35 V to 36 V at 37 V, and tuned the program/erase current ratio from about 38 to about 39. The same device family showed six different current levels and at least 40-bit storage in one device (Zhang et al., 2014).
Pulse studies in that architecture used 41 V programming and 42 V erasing, with pulse widths from 43 ms to 44 s for dynamic threshold-shift analysis and 45 ms for endurance cycling. The extracted stored electron density was approximately 46, the stored hole density approximately 47, and the charge-trapping rate varied from about 48 to 49 as pulse width increased from 50 ms to 51 s. The threshold shift in retention experiments decreased from 52 V to 53 V after 54 s, leading to a projected charge loss of about 55 after 56 years, while endurance was demonstrated over 57 cycles (Zhang et al., 2014).
The fully 2D monolayer MoS58/graphene memory reported a maximum threshold shift or memory window of about 59 V for control-gate sweeps up to about 60 V, a program/erase current ratio greater than 61, and a stored electron density of about 62. Dynamic switching was shown with 63 V, 64 ms pulses at 65 mV, endurance exceeded 66 cycles, and extrapolation from the threshold-voltage decay suggested that about 67 of the initial stored charge would remain on the floating gate after 68 years (Bertolazzi et al., 2013).
A later benchmark from the transferable black-phosphorus AHA stack sharpened the comparative context. That study reported a memory window exceeding 69 V from 70 V sweeps, projected 71–72 charge loss after 73 years, and explicitly stated that the compared MoS74 flash memory showed 75 loss after 76 years. Its broader relevance lies less in the black-phosphorus channel than in the demonstration that a thin Al77O78 tunnel oxide plus HfO79 trap layer can support large windows and strong retention in a 2D memory geometry (Feng et al., 2015).
5. Boundary cases and related MoS80 memory phenomena
Not every nonvolatile or hysteretic MoS81 device is a charge-trap memory in the strict sense. The surrounding literature contains several adjacent mechanisms that either mimic charge-trap memory or illuminate its failure modes.
| Class | Representative papers | Distinguishing storage variable |
|---|---|---|
| Conventional charge-storage transistor memory | (Zhang et al., 2014, Bertolazzi et al., 2013) | HfO82 trap occupancy or isolated floating-gate charge |
| Persistent optoelectronic / photodoping memory | (Roy et al., 2013, Gadelha et al., 2020) | Long-lived charge separation or trapped interfacial charge written optically |
| Defect- or ion-mediated memory | (Sleziona et al., 2023, Mallik et al., 2023, Zhou et al., 23 Jan 2026) | Oxide traps, Na83 migration in SiO84, or mobile oxygen vacancies in HfO85 |
| Memristive resistive switching | (Sangwan et al., 2015, Sangwan et al., 2018) | Grain-boundary or sulfur-vacancy redistribution and contact-barrier modulation |
| Volatile capacitor memory | (Liao et al., 2019) | Charge on an explicit storage capacitor, with MoS86 only as access transistor |
Graphene/MoS87 persistent photoconductivity memory demonstrated an optically written, electrically erased state with essentially no measurable decay over three decades in time at low photoexcitation intensity, stability over more than 88 hours, and rewriteability over days with better than 89 accuracy, but it had no tunnel oxide, no blocking oxide, and no engineered trap layer; the state was attributed to localized holes in MoS90 sustaining excess electrons in graphene (Roy et al., 2013). A different MoS91/BN/graphite photomemory shifted the threshold from about 92 V to about 93 V, extracted 94, achieved 95 up to 96 at negative read gate bias, and extrapolated about 97 photocurrent retention after 98 years, but it attributed storage to trapped holes at the graphite/BN interface and required optical excitation for both write and erase (Gadelha et al., 2020).
Defect-engineered back-gated MoS99 FETs can also act as memory without a dedicated storage layer. Xe00 irradiation at 01 keV converted nearly non-hysteretic monolayer MoS02/SiO03 transistors into long-relaxation hysteretic memories; the hysteresis height increased linearly with ion fluence, the current hysteresis reached about two orders of magnitude at the highest fluence, and transient fits gave 04 s and 05 s, with the active storage medium interpreted mainly as negatively charged irradiation-induced oxide defects in SiO06 (Sleziona et al., 2023). In another direction, thermally driven monolayer MoS07/SiO08/Si mem-transistors grown by NaCl-assisted CVD showed weak clockwise hysteresis below room temperature but anti-clockwise hysteresis and multilevel nonvolatile states above about 09 K; at 10 K, 11 reached 12, the READ/RESET ratio reached about 13, and distinct levels remained discernible for 14 s, with the mechanism assigned to gate-field-modulated Na15-ion dynamics and charge transfer at the MoS16/dielectric interface (Mallik et al., 2023).
Memristive MoS17 devices form a separate branch. Grain-boundary-mediated monolayer devices showed switching ratios up to 18 with gate-tunable set voltage, while later polycrystalline monolayer memristors showed switching ratios up to about 19 and threshold-voltage shifts of about 20–21 V, but both works treated the internal state primarily as vacancy migration, grain-boundary dynamics, or contact-barrier modulation rather than storage in a dedicated trap medium (Sangwan et al., 2015, Sangwan et al., 2018). By contrast, dual-gated MoS22 DRAM used a 23T24C architecture with a storage capacitor and achieved 25 ms retention by suppressing access-transistor leakage; its memory state was capacitor charge, not trapped charge in MoS26 or its gate dielectric (Liao et al., 2019).
6. Methodological issues, misconceptions, and design directions
A persistent misconception in the MoS27 memory literature is to equate transfer-curve hysteresis with intentional charge-trap memory. Pulse-based and environment-controlled measurements show why that inference is unreliable. In salt-assisted CVD monolayer MoS28 FETs on 29 nm SiO30, hysteresis in air reached about 31 V for a 32 to 33 V sweep, but high vacuum reduced it by about 34; amplitude-sweep pulse 35–36 measurements with 37 ms pulses yielded essentially hysteresis-free transfer characteristics and increased the apparent mobility from 38 to 39, while single-pulse transients separated a fast trapping component with 40–41 s from a slow component with 42–43 s (Mallik et al., 2020).
High-bias transport studies further show that MoS44 itself can be an unintended trap reservoir. Short-channel monolayer devices on 45 nm SiO46 exhibited trap-assisted space-charge-limited current with an exponential trap distribution,
47
and a temperature-independent critical voltage
48
from which the trap density was extracted as about 49 to 50 (Ghatak et al., 2013). This implies that a measured memory window in a MoS51 transistor can include contributions from channel-localized traps, not only from an intended storage layer.
At the dielectric level, HfO52 and Al53O54 diverge sharply under stress and temperature. Similar back-gated monolayer MoS55 FETs with about 56 nm HfO57 or Al58O59 both showed sizeable clockwise hysteresis at room temperature, but at 60C the HfO61 devices developed dominant counterclockwise hysteresis, negative 62 shift, self-doping, and negative differential resistance, which a compact model attributed to mobile positively charged oxygen vacancies drifting in HfO63. Al64O65 devices displayed only minor counterclockwise dynamics even at 66C. The study explicitly framed this as an insulator-selection paradigm: Al67O68 is better suited to suppress detrimental negative 69 shifts in MoS70 logic FETs at high temperatures, whereas HfO71 can serve as an active memory layer that exploits these abnormal instabilities (Zhou et al., 23 Jan 2026).
A plausible implication is that MoS72 charge-trap memory research is organized around a recurring balance. On one side is the deliberate use of high-73 stacks, floating gates, or engineered interfaces to obtain large memory windows, strong retention, and multilevel states. On the other is the need to exclude parasitic storage in adsorbates, channel traps, substrate oxide traps, mobile ions, or grain-boundary defect networks. The most robust results in the literature therefore combine architectural control of the storage medium with diagnostics that discriminate intentional nonvolatile storage from transient or defect-mediated hysteresis.