Threshold-Programmable FETs

• Threshold-programmable FETs are devices whose channel voltage is adjusted post-fabrication using engineered doping, ferroelectric polarization, and fluidic or charge-based modulation.
• They employ methods like work-function engineering and dynamic body biasing to achieve non-volatile or reversible voltage shifts, crucial for low-power logic, secure applications, and neuromorphic systems.
• Integrating these FETs enables in-field configurability and camouflaged logic circuits, offering enhanced reconfigurability, robust performance metrics, and resistance to reverse-engineering.

Threshold-programmable field-effect transistors (FETs) are a class of devices in which the channel threshold voltage ($V_{th}$) can be precisely adjusted post-fabrication—either permanently or reversibly—via physical, chemical, or electrical means. This capability enables dynamic or in-field configurability of logic, memory, analog, and security primitives, extending the traditional role of the FET beyond static, process-defined characteristics. Techniques for threshold programming span from channel doping and work-function engineering to ferroelectric polarization control, fluidic or charge-based field effects, and active body biasing. Ongoing developments establish threshold programmability as fundamental in low-power logic, secure hardware, non-volatile memory, and neuromorphic systems.

1. Physical Mechanisms and Device Architectures

Multiple physical mechanisms underlie threshold-programmable FETs, each dictating device geometry, programming resolution, volatility, and application domain.

1.1. Doping and Work-Function Engineering

Classic "threshold voltage-defined (TVD)" FETs leverage engineered channel doping and metal gate work-function selection to assign high- or low-$V_{th}$ states. HVT/LVT devices are realized via implant masks or localized work-function adjustment. Once set during front-end-of-line processing, these thresholds are permanent (Iyengar et al., 2015).

1.2. Ferroelectric Polarization Control

Ferroelectric-gate FETs (FeFETs) employ polarization switching in a ferroelectric layer (e.g., Hf$_{0.5}$Zr$_{0.5}$O$_2$ or Al$_{0.68}$Sc$_{0.32}$N) to dynamically shift $V_{th}$ after fabrication. Each polarization state induces a remanent charge at the interface, modulating the channel electrostatics (Lu et al., 2020, Rhee et al., 2024). The effect is robust and non-volatile, enabling multi-level or binary operation.

1.3. Electrochemical and Fluidic Modulation

Ion-sensitive FETs (ISFETs) utilize changes in the ionic environment at the gate dielectric to affect surface potential, and consequently $V_{th}$, providing field/configuration reprogrammability without altering the solid-state device (Moussavi et al., 2023).

1.4. Field and Charge-Induced Programming

Charge-trapping in dielectric stacks, as exploited in electron-beam programmable 2D FETs (e.g., WSe$_2$ on hBN/Al$V_{th}$0O$V_{th}$1), enables rewritable and site-selective $V_{th}$2 tuning via external stimulus, with patterning at sub-micrometer resolution (Lan et al., 6 Dec 2025).

1.5. Dual-Gate and Body Bias

Flexible-FETs and body-biasing architectures (e.g., DTMOS/VTMOS) actively modulate the channel potential barrier via a back-gate, substrate bias, or dynamic connection schemes, imparting electrical control over $V_{th}$3 at runtime (Chowdhury et al., 2012, Ragini et al., 2010).

Programming Paradigms Table

Mechanism	Modality	Volatility / Endurance
Channel doping/work-func.	One-time	Permanent
Ferroelectric switching	Multi-level	Non-volatile, $V_{th}$4 cycles
ISFET ion exchange	Reversible	Quasi-volatile, $V_{th}$510 h retention
Charge trapping (e-beam)	Rewritable	Reversible, $V_{th}$6 cycles
Body bias / Flexible-FET	Dynamic	Volatile (active only)

2. Analytical Models and Threshold Shift Equations

Threshold programming requires rigorous control and predictability of $V_{th}$7 modulation. Key mathematical formalisms relate the device parameters, structural features, and external stimuli to the resultant $V_{th}$8.

2.1. Doping/Work-Function Based $V_{th}$9

In bulk MOSFETs: $_{0.5}$0 where $_{0.5}$1 is the gate-to-channel work-function difference, $_{0.5}$2 is the body-effect coefficient, and $_{0.5}$3 is the source–body bias. HVT/LVT flavors differ by $_{0.5}$4–$_{0.5}$5 V (Iyengar et al., 2015).

2.2. Ferroelectric/Gate Polarization

For FeFETs, the threshold shift due to polarization $_{0.5}$6: $_{0.5}$7 or, for a multi-stack: $_{0.5}$8 where $_{0.5}$9, $_{0.5}$0 are (ferro)electric capacitances per unit area (Lu et al., 2020, Rhee et al., 2024).

2.3. Electrochemical/ISFET

ISFET $_{0.5}$1 includes a pH-dependent surface potential: $_{0.5}$2 with ideal Nernstian response yielding $_{0.5}$359 mV/pH at 25°C (Moussavi et al., 2023).

2.4. Charge-Trapping (e-beam)

Modulated threshold in charge-trap FETs: $_{0.5}$4 with $_{0.5}$5 directly controlled by patterning (Lan et al., 6 Dec 2025).

2.5. Flexible-FET Dual Gate

Closed-form $_{0.5}$6 in Flexible-FETs: $_{0.5}$7 (Chowdhury et al., 2012).

3. Device Fabrication, Programming Workflows, and Performance Metrics

3.1. Fabrication Flow

• Doping/work-function: Defined at mask/litho level, no post-process adjust.
• Ferroelectric: Integration of a 10–45 nm ferroelectric layer by ALD or PVD, annealed for crystallinity, with pulse-based programming post-fab (Lu et al., 2020, Rhee et al., 2024).
• ISFET: Standard CMOS flow, finished with Si$_{0.5}$8N$_{0.5}$9/Al$_2$0O$_2$1 passivation; gate set post-fab by ionic solution application (Moussavi et al., 2023).
• 2D e-beam: Monolayer semiconductor (e.g., WSe$_2$2), encapsulated in hBN, patterned and voltage-modulated under e-beam exposure (Lan et al., 6 Dec 2025).
• Flexible-FET/DTMOS: SOI double-gate with self-aligned bottom-gate; substrate or gate voltage source for dynamic $_2$3 tuning (Chowdhury et al., 2012, Ragini et al., 2010).

3.2. Programming Protocols

• FeFET: 1 μs programming pulses (2.6–7.6 V for HZO), up to 27 resolvable $_2$4 levels, programming window $_2$51.3 V (Lu et al., 2020).
• ISFET: $_2$6 switched by exposure to pH 2–10 buffers; ∼30 s equilibration, 470 mV $_2$7 shift achievable, retention $_2$810 h, $_2$9 cycles (Moussavi et al., 2023).
• e-beam: 10–60 s exposure, writing $_{0.68}$0 up to $_{0.68}$18.5 V, retention $_{0.68}$224 h (Lan et al., 6 Dec 2025).
• DTMOS/VTMOS: $_{0.68}$3 swept 0–0.2 V; voltage bias sets dynamic threshold, active only under supply (Ragini et al., 2010).

3.3. Performance Metrics

• On/off ratio: $_{0.68}$4–$_{0.68}$5 (TVD, FeFET, SWCNT FeFET), up to $_{0.68}$6 (e-beam WSe$_{0.68}$7).
• Endurance: $_{0.68}$8 (ferroelectric, TVD), $_{0.68}$9 (ISFET), $_{0.32}$0 (e-beam).
• Read/program speed: 1–25 ns (ferroelectric), $_{0.32}$1 ms (ISFET verify), $_{0.32}$2 s (e-beam write).
• Retention: Non-volatile (FeFET, e-beam), %%%%57$V_{th}$058%%%% s (SWCNT FeFET), $_{0.32}$510 h (ISFET).
• Power/delay: VTMOS allows sub-300 pW per gate at $_{0.32}$6=0.2 V, 50% power reduction vs. CMOS at $_{0.32}$7 MHz (Ragini et al., 2010).

4. Circuit-Level Applications and Architectural Integration

4.1. Camouflaged and Reconfigurable Logic

• TVD and ISFET-TVD gates achieve universal logic (NAND/NOR/AND/OR/XOR/XNOR/INV/BUF) by selective HVT/LVT assignment, obscuring function from physical layout (Iyengar et al., 2015, Moussavi et al., 2023).
• FeFET and e-beam-written FETs enable in-field logic reconfiguration and hardware personalization; rewritable logic (e.g., NAND↔NOR) is demonstrated with threshold-polarity transitions (Lan et al., 6 Dec 2025).
• Flexible-FET and DTMOS/VTMOS enable adaptive logic where sub-threshold operation can dynamically vary the logic thresholds for energy efficiency (Ragini et al., 2010).

4.2. Neuromorphic and Memory Functions

• Multi-level threshold FeFETs function as artificial synapses for deep neural network online training, achieving $_{0.32}$898% MNIST accuracy using device-level weight updates (Lu et al., 2020).
• Mott-FeFETs exploit an insulator-metal transition for decoupled program/read margins, $_{0.32}$9, and low-voltage operation (Vaidya et al., 2021).
• SWCNT/AlScN FeFETs realize compact, back-end-of-line-compatible ternary content-addressable memory with a single FET per cell, reducing area by 10$V_{th}$0 over CMOS implementations (Rhee et al., 2024).

5. Materials, Interface Engineering, and Scalability

• Work-function engineering with low-defect dielectrics (e.g., ZrO$V_{th}$1/hBN) allows precise, tunable $V_{th}$2 in monolayer MoS$V_{th}$3 FETs, circumventing pinning observed in HfO$V_{th}$4 (Liu et al., 23 Dec 2025).
• Standard ALD/PVD and transfer processes support integration of ferroelectric films and aligned nanomaterials (SWCNTs, 2D TMDs), with BEOL compatibility (T$V_{th}$5400$V_{th}$6C) (Rhee et al., 2024).
• Interface chemistry (low $V_{th}$7, minimal $V_{th}$8) is critical for achieving linear and reproducible $V_{th}$9 modulation, especially in gate-stack and 2D FETs (Liu et al., 23 Dec 2025).
• Fluidic and e-beam programming depend on charge-trap stability and environmental retention; volatile modes are suited to tamper-evidence or temporary logic reconfiguration.

6. Security and Hardware Obfuscation

• Threshold-programmable switches in TVD/ISFET-TVD cells resist physical/netlist reverse engineering, as $V_{th}$0 state is invisible to standard imaging (Iyengar et al., 2015, Moussavi et al., 2023).
• ISFET-TVD provides post-manufacture personalization (hardware PUFs, in-field role transformation) by re-exposing passivation to alternate pH solutions (Moussavi et al., 2023).
• Even a modest fraction of gates implemented as threshold-programmable (e.g., 1% out of 10k gates) yields brute-force security times exceeding $V_{th}$1 years at 1 GHz test rates (Iyengar et al., 2015).

7. Limitations and Future Directions

• Ferroelectric devices, while non-volatile, may exhibit endurance limits ($V_{th}$2–$V_{th}$3 cycles) and require high programming voltages (typically $V_{th}$42–4 V), although SWCNT/FeFET and Mott-FeFET examples show progress on voltage scaling (Vaidya et al., 2021, Rhee et al., 2024).
• ISFET fluidic programming is limited by retention ($V_{th}$510 h) and surface chemical drifts (≈5–10 mV per decade), but enables field-reconfigurability not feasible with implanted-doping-based TVD (Moussavi et al., 2023).
• Dynamic body-biasing (VTMOS/DTMOS) and Flexible-FETs deliver ultra-low-power operation at the expense of speed, area, and reliability overhead for body-bias generation (Ragini et al., 2010).
• A key research focus is extension to 2D materials (WSe$V_{th}$6, MoS$V_{th}$7) where native interfaces allow threshold tuning without chemical doping, defect manipulation, or high-temperature processing (Liu et al., 23 Dec 2025, Lan et al., 6 Dec 2025).
• Integration, uniformity, and scaling challenges are prominent in large-area arrays and in co-design for neuromorphic and security primitives.

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See: (Lu et al., 2020, Rhee et al., 2024, Moussavi et al., 2023, Iyengar et al., 2015, Chowdhury et al., 2012, Vaidya et al., 2021, Liu et al., 23 Dec 2025, Lan et al., 6 Dec 2025, Ragini et al., 2010).