Flash Memory: Principles & Innovations

• Flash memory is a non-volatile storage technology utilizing cells with multiple voltage levels, where programming is incremental and erasure occurs at block level.
• It leverages techniques such as incremental step pulse programming, dynamic voltage allocation, and constrained coding to balance capacity, performance, and reliability.
• Emerging innovations integrate novel materials and adaptive controllers to mitigate wear, reduce errors, and extend the endurance of flash-based devices.

Flash memory is a non-volatile computer memory comprised of blocks of cells, wherein each cell can take on $q$ different values or levels; increasing the cell level is easy, but reducing the level of a cell can be accomplished only by erasing an entire block (Yaakobi et al., 2012). In contemporary systems, NAND flash is the dominant storage technology in modern SSDs, used across data centers and mobile devices, while NOR flash remains important as stand-alone memory and embedded memory (Mutlu et al., 2018, Feng et al., 2024). Across device physics, controller architecture, coding theory, and system software, the defining technical problem is the same: exploiting the asymmetry between programming and erasure to maximize capacity, performance, and lifetime before block erasures, disturb effects, retention loss, or oxide degradation become limiting.

1. Physical model and operating principles

Flash memory is commonly discussed in two architectural families. NOR is preferable for code execution because of low read latencies and byte-addressability; NAND is favored for bulk data storage thanks to higher density, better I/O throughput, and lower cost per bit (Olivier et al., 2012). In NAND flash, organization is hierarchical: planes, blocks, and pages. Contemporary blocks contain 64–128 pages; pages are typically 2–8 KB, and each page includes a user-data region plus an Out-Of-Band area for metadata such as bad-block markers and ECC (Olivier et al., 2012). A complementary embedded-Linux study reports a representative geometry of 64 pages per block and 2048-byte pages (Olivier et al., 2012).

At the cell level, NAND flash stores data as charge in floating-gate or charge-trap cells. The logical value is encoded by a threshold voltage $V_{th}$ in a device-defined window $[V_{\min},V_{\max}]$ and sensed by one or more reference voltages $V_{\mathrm{ref}}$ (Choi et al., 2017). SLC uses two non-overlapping voltage ranges to store one bit per cell, whereas MLC and TLC use 4 and 8 states to store 2 and 3 bits per cell, respectively (Choi et al., 2017). This multi-level signaling is one reason flash memory has continued to increase density, but it narrows read margins and intensifies sensitivity to variability.

Programming and erasure are intrinsically asymmetric. Reads and writes occur at page granularity, while erases occur at block granularity; consequently, in-place updates are impossible and updates are written out of place, with invalid data later reclaimed by garbage collection (Olivier et al., 2012). In NAND, programming commonly uses incremental step pulse programming, a staircase of fixed-duration voltage pulses with verify after each step to reach a target threshold voltage. To first order,

$$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$

This relation underlies several controller-level and coding-level optimizations that trade threshold placement, retention, and endurance (Choi et al., 2017).

A large theoretical literature abstracts the same asymmetry in terms of monotone state evolution. In rewriting-code models, a flash block state is a vector in $\{0,1,\dots,q-1\}^n$, transitions are allowed only when each component is non-decreasing, and the total number of available level transitions is $n(q-1)$ [(Anxiao et al., 2010); (Yaakobi et al., 2012)]. This abstraction is not merely formal. It captures the same engineering constraint that governs practical NAND and NOR devices: every useful write consumes a finite physical budget of level transitions before an erase becomes unavoidable.

2. Scaling, interference, and reliability limits

A recurrent misconception is that flash-memory scaling is primarily a density problem. The literature instead treats reliability and lifetime as the central scaling challenge. Aggressive process technology scaling and multi-level cell technology improve capacity, but they raise raw bit error rates and exacerbate process variation; because ECC has an upper bound on the number of raw bit errors it can correct, SSDs have a finite lifetime, and typical SSD lifetime has fallen by 1–2 orders of magnitude over the last decade (Mutlu et al., 2018).

Three error families dominate the contemporary NAND reliability discussion. First, retention errors arise because stored charge is lost over time, causing retention-induced bit errors that accumulate as the device ages (Mutlu et al., 2018). Second, read disturb occurs because read operations introduce errors in other, unread portions of the memory, and the effect accumulates with use (Mutlu et al., 2018). Third, two-step programming in state-of-the-art devices can create data vulnerabilities that can be exploited by malicious applications to cause data corruption or leakage (Mutlu et al., 2018). SAFARI’s summaries emphasize both runtime mitigation and post-failure data-recovery mechanisms for retention and read disturb, and three protections for two-step programming vulnerabilities, although the editorial overview deliberately omits algorithmic details and quantitative overheads (Mutlu et al., 2018).

Inter-cell interference provides a complementary channel model for these reliability limits. In scaled NAND, capacitive coupling among neighboring cells perturbs the victim threshold voltage according to

$$\Delta V_{\mathrm{th,ICI}}(i,j)=\gamma_x(\Delta V(i,j-1)+\Delta V(i,j+1))+\gamma_y(\Delta V(i-1,j)+\Delta V(i+1,j))+\gamma_{xy}(\cdots),$$

where the coupling ratios reflect parasitics along bitline, wordline, and diagonal directions (Kim et al., 2014). As lithography scales, these coupling coefficients increase, and the same absolute $\Delta V_{th}$ consumes a larger fraction of the read margin in MLC, TLC, QLC, and PLC than in SLC (Kim et al., 2014). The same paper recasts the flash channel as a “dirty flash memory” problem and shows that a single pre-read can convert interference into a memory-with-defective-cells model, enabling additive encoding that significantly lowers the probability of decoding failure (Kim et al., 2014).

At the channel-model level, wear and retention can also be expressed through explicit noise terms. One information-theoretic formulation models the read threshold as

$y=x+n_p+n_w+n_r,$

where $V_{th}$0 is programming noise, $V_{th}$1 is wear-out noise, and $V_{th}$2 is retention noise (Chen et al., 2014). In that model, the accumulated programmed-threshold budget

$V_{th}$3

drives the wear-out and retention-noise parameters (Chen et al., 2014). This suggests that modern flash reliability is not reducible to a single “endurance number”: it is a coupled problem involving raw-error growth, disturb, parasitic coupling, and the amount of charge moved through the oxide over time.

3. Endurance-oriented programming and controller mechanisms

One influential controller-level observation is that enterprise and OLTP storage-class-memory data are often short-lived relative to the retention guarantee of flash. On a 64 GB SLC SSD fronting SCM and evaluated with 15 write-intensive MSR Cambridge traces, more than 90% of written data have longevity up to 10 hours, while flash vendors guarantee retention up to approximately 10 years (Choi et al., 2017). Dense-SLC exploits this mismatch by relaxing retention and allowing multiple writes into a cell during each erase cycle. In 4-state mode, it yields page writes per erase $V_{th}$4; in 8-state mode, it yields $V_{th}$5 (Choi et al., 2017). The governing drift model is

$V_{th}$6

and the controller assigns blocks to 2-state, 4-state, or 8-state modes according to block age and required retention (Choi et al., 2017). In simulation, D-SLC improves SSD lifetime by 5.1$V_{th}$7–8.6$V_{th}$8 across workloads, 6.8$V_{th}$9 on average, with no performance penalty; throughput increases modestly, by about 3% on average, GC overhead is reduced by about 9.7% in invocation rate and about 6.3% in cost, and average scrubbing rate is approximately 0.071% of allocated blocks (Choi et al., 2017).

A distinct endurance mechanism treats the flash read channel as a noisy channel whose instantaneous mutual information should be held just above the ECC requirement. The proposed dynamic-voltage-allocation scheme scales program targets and read thresholds with a parameter $[V_{\min},V_{\max}]$0 so that instantaneous capacity remains near a fixed target. In the reported 4-level MLC example, the target is 1.92 bits/cell for a rate-8/9 LDPC code, $[V_{\min},V_{\max}]$1 is adjusted every 100 P/E cycles, the baseline fixed-level design reaches 1.9 bits/cell at about 3000 P/E cycles, and the adaptive scheme extends lifetime to approximately 5400 P/E cycles, an approximately 80% improvement at 1-year retention (Chen et al., 2014). The technical significance is that lifetime is extended not by stronger codes alone, but by reducing early-life overprogramming and the associated growth of wear-out and retention noise.

NOR flash has recently been pushed much further through operation-scheme optimization rather than new device geometry. In 55 nm planar NOR floating-gate flash, program is performed by channel hot electron injection and erase by hot hole injection, both with 20 ns pulses; the endurance-oriented operating point uses a reduced memory window of about 0.2 V and a high-$[V_{\min},V_{\max}]$2 mode with programmed $[V_{\min},V_{\max}]$3 V instead of a low-$[V_{\min},V_{\max}]$4 mode near 4 V (Feng et al., 2024). An electric-field-assisted relaxation pulse of approximately 0.5 V and 20 ns is applied immediately after each erase. Under this combined CHEI + HHI + EAR scheme, endurance reaches $[V_{\min},V_{\max}]$5 P/E cycles, off-state leakage remains sub-10 pA after $[V_{\min},V_{\max}]$6 cycles, and after up to $[V_{\min},V_{\max}]$7 erase pulses the devices with EAR exhibit subthreshold swing of about 334 mV/dec and $[V_{\min},V_{\max}]$8 pA (Feng et al., 2024). This result is notable because it shows that waveform engineering, threshold-mode selection, and post-erase relaxation can transform endurance without changing cell area or basic process integration.

Taken together, these mechanisms establish a broader pattern. Retention time, programmed charge, and erase stress are not fixed material constants at the system level; they are resources that controllers can budget, relax, or redistribute.

4. Rewriting codes, constrained codes, and erasure-efficient data movement

Coding theory formalizes flash asymmetry as a rewrite-limited medium. An $[V_{\min},V_{\max}]$9 flash code stores $V_{\mathrm{ref}}$0 information bits in $V_{\mathrm{ref}}$1 $V_{\mathrm{ref}}$2-ary cells and guarantees $V_{\mathrm{ref}}$3 writes before a block erasure becomes necessary; the write deficiency is

$V_{\mathrm{ref}}$4

which measures how far a code is from perfectly utilizing all available level transitions (Yaakobi et al., 2012). For large $V_{\mathrm{ref}}$5, one construction achieves write deficiency $V_{\mathrm{ref}}$6 if $V_{\mathrm{ref}}$7, and at most $V_{\mathrm{ref}}$8 otherwise (Yaakobi et al., 2012). A related trajectory-code framework generalizes WOM codes, floating codes, and buffer codes through a directed data graph, and proves asymptotic optimality in a wide range of scenarios (Anxiao et al., 2010).

The multidimensional-flash-code construction extends the earlier Jiang–Bruck two-bit ideas to arbitrary numbers of bits by organizing cells into recursively structured blocks. For $V_{\mathrm{ref}}$9 bits and odd $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$0, the resulting deficiency bound is

$$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$1

and, crucially, the bound is independent of $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$2 (0901.0702). This makes the family asymptotically optimal in the sense that write efficiency approaches 1 as $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$3 grows for fixed $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$4 and $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$5 (0901.0702).

Constrained coding targets a different physical bottleneck: asymmetric inter-cell interference in high-level cells. QA-LOCO codes forbid patterns in which a highest-level cell $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$6 flanks lower-level neighbors, such as $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$7 when $$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$8 and, more generally, the family

$$T_{\mathrm{PROG}} \propto \frac{V_{\mathrm{target}}-V_{\mathrm{start}}}{V_{\mathrm{ISPP}}}.$$9

with $\{0,1,\dots,q-1\}^n$0 (Hareedy et al., 2020). For $\{0,1,\dots,q-1\}^n$1, QA-LOCO codes can achieve rates greater than $\{0,1,\dots,q-1\}^n$2 information bits per coded symbol, while remaining reconfigurable as problematic patterns evolve with device age (Hareedy et al., 2020). In effect, they shift some of the reliability burden from post hoc ECC to write-time pattern avoidance.

Coding also improves wear leveling during large-scale data movement. In the flash data movement problem, sorting-based non-coding schemes require at least $\{0,1,\dots,q-1\}^n$3 erasures to move data among $\{0,1,\dots,q-1\}^n$4 blocks, whereas coding-based schemes require only $\{0,1,\dots,q-1\}^n$5 erasures; the coding-based schemes use only one auxiliary block, which is the best possible, and a GF(2) XOR-based algorithm uses exactly $\{0,1,\dots,q-1\}^n$6 erasures with balanced wear across the $\{0,1,\dots,q-1\}^n$7 blocks (0911.3992). This is a direct example of coding reducing physical wear rather than merely increasing logical capacity.

These results collectively refute another common simplification: flash coding is not only about correcting errors after the fact. In the flash literature, codes are also used to defer erasures, shape admissible patterns, rebalance wear, and translate application-level rewrites into physically legal monotone transitions.

5. Flash translation layers, flash file systems, and flash-aware data structures

At the system level, flash memory is managed either by a flash translation layer hidden inside SSDs, SD cards, and USB drives, or by native flash file systems operating directly on raw NAND through Linux MTD (Olivier et al., 2012). In raw-NAND embedded systems, the major Linux-native flash file systems are JFFS2, YAFFS2, and UBIFS [(Olivier et al., 2012); (Olivier et al., 2012)]. JFFS2 and YAFFS2 rebuild metadata by scanning the partition and therefore have mount time and RAM consumption that scale linearly with flash size, whereas UBIFS uses tree-based indexing and scales as $\{0,1,\dots,q-1\}^n$8 with partition size at the file-system layer (Olivier et al., 2012). In benchmarking, YAFFS2 can be about $\{0,1,\dots,q-1\}^n$9 faster than JFFS2 and UBIFS on metadata search, with the find command taking about 1 s versus about 2.5 s across 2,000 files, while JFFS2 can be about $n(q-1)$0 faster than YAFFS2 on deletion, roughly 0.8 s versus roughly 4 s in a comparable 2,000-file case (Olivier et al., 2012). UBIFS consistently shows the best mount times in the reported study (Olivier et al., 2012).

Garbage collection in flash-resident page-mapping FTLs poses a distinct metadata problem because the physical address of the before-image may be unknown at write time when the mapping entry is not cached. Lazy Gecko addresses this by maintaining a Page Validity Bitmap in RAM and a flash-resident reverse map; Logarithmic Gecko stores the same bitmap in flash as an LSM-tree, sharply reducing RAM demand (Dayan et al., 2015). For a Micron P420m-like geometry, the RAM-resident PVB is about 16 MB, whereas Logarithmic Gecko’s total RAM footprint is approximately 482 KB; for an Intel 525-like geometry, the corresponding figures are about 1 MB and about 112 KB, or about 3% and about 11% of Lazy Gecko’s RAM usage in the two device examples (Dayan et al., 2015). The price is modest I/O overhead: the LSM-tree write contribution is not greater than 3% in the reported experiments (Dayan et al., 2015).

Flash-aware data structures extend the same logic above the file-system layer. The FM Tree stores nodes in flash pages, does not require in-node key arrays to remain sorted, uses lazy erasures and “barren” markers for logical removal, and rebuilds compact structure during garbage collection rather than through erase-heavy immediate rebalancing (III et al., 2012). In emulation, it extends the operational lifespan of each block of flash memory by a factor of roughly 27 to 70 times while still supporting logarithmic-time search tree operations (III et al., 2012). This suggests that flash asymmetry is not only a controller or code-design issue; it can profitably reshape classical data structures.

6. Emerging device concepts and material platforms

Beyond conventional NAND and NOR, several lines of work explore how alternative materials modify the flash trade space among speed, retention, leakage, and process temperature. One approach uses a two-terminal intrinsic charge-trap capacitive memory based on solution-derived aluminum oxide phosphate, with no tunneling layer and no blocking layer. In this MIS capacitor, the ALPO layer simultaneously provides intrinsic traps and low leakage, with reported trap densities above $n(q-1)$1 and leakage current density $n(q-1)$2 at $n(q-1)$3 (Mondal et al., 2019). Trap density is tunable by post-deposition heating: the memory window changes from approximately 17.5 V at 200$n(q-1)$4C to approximately 0.7 V at 800$n(q-1)$5C, corresponding to a 96% reduction in trap density relative to the low-temperature high-trap films (Mondal et al., 2019). The devices show program/erase speed of about 200 ms, a single-pulse memory window of about 9 V, no degradation over $n(q-1)$6 P/E cycles, and negligible degradation of C–V hysteresis after 5 years of ambient storage (Mondal et al., 2019).

A second direction uses carbon nanomaterials in floating-gate transistors. The proposed multilayer-graphene-nanoribbon and carbon-nanotube floating-gate transistor replaces the silicon channel with multilayer graphene nanoribbon and the polysilicon floating gate with a CNT layer (Hossain et al., 2015). Its electrostatics are described by a floating-gate capacitance network with

$n(q-1)$7

and a Fowler–Nordheim tunneling current

$n(q-1)$8

where $n(q-1)$9 (Hossain et al., 2015). The reported analysis argues that the proposed graphene-based floating-gate transistor could be operated at a reduced voltage compared to conventional silicon based floating-gate devices because the same control-gate bias produces a larger floating-gate potential (Hossain et al., 2015).

A third direction uses van der Waals heterostructures. In a MoS$$\Delta V_{\mathrm{th,ICI}}(i,j)=\gamma_x(\Delta V(i,j-1)+\Delta V(i,j+1))+\gamma_y(\Delta V(i-1,j)+\Delta V(i+1,j))+\gamma_{xy}(\cdots),$$0/h-BN/multilayer-graphene stack with atomically flat interfaces, the reported device achieves approximately 20 ns write and erase, surpassing the approximately 100 ns reported for advanced Si-based floating-gate flash (Liu et al., 2020). The main device uses about 10.5 nm h-BN, exhibits a 53 V memory window at $$\Delta V_{\mathrm{th,ICI}}(i,j)=\gamma_x(\Delta V(i,j-1)+\Delta V(i,j+1))+\gamma_y(\Delta V(i-1,j)+\Delta V(i+1,j))+\gamma_{xy}(\cdots),$$1 V when the back gate is swept between $$\Delta V_{\mathrm{th,ICI}}(i,j)=\gamma_x(\Delta V(i,j-1)+\Delta V(i,j+1))+\gamma_y(\Delta V(i-1,j)+\Delta V(i+1,j))+\gamma_{xy}(\cdots),$$2 V, stores an areal charge density of about $$\Delta V_{\mathrm{th,ICI}}(i,j)=\gamma_x(\Delta V(i,j-1)+\Delta V(i,j+1))+\gamma_y(\Delta V(i-1,j)+\Delta V(i+1,j))+\gamma_{xy}(\cdots),$$3, shows an on/off ratio greater than $$\Delta V_{\mathrm{th,ICI}}(i,j)=\gamma_x(\Delta V(i,j-1)+\Delta V(i,j+1))+\gamma_y(\Delta V(i-1,j)+\Delta V(i+1,j))+\gamma_{xy}(\cdots),$$4 immediately after ultrafast operation, and retains 50.6% and 50.4% of the initial threshold difference at $$\Delta V_{\mathrm{th,ICI}}(i,j)=\gamma_x(\Delta V(i,j-1)+\Delta V(i,j+1))+\gamma_y(\Delta V(i-1,j)+\Delta V(i+1,j))+\gamma_{xy}(\cdots),$$5 s, corresponding to 10 years, while demonstrating endurance of 1185 program/erase cycles (Liu et al., 2020). The physical rationale is that atomically flat interfaces suppress interface charge states and trap-assisted tunneling while maintaining sufficiently strong tunneling through h-BN under high field (Liu et al., 2020).

Across these emerging devices, the main technical lesson is not that conventional flash has been superseded. Rather, the literature points to multiple viable axes of innovation: controller-centric waveform optimization in mature NOR, retention-aware state placement in NAND, and material redesign in low-temperature oxides, graphene/CNT stacks, and vdW heterostructures. SAFARI’s broader conclusion is that careful characterization, behavior-driven modeling, and low-cost architecture or firmware mechanisms are likely to remain useful even as attention shifts to emerging nonvolatile memories such as PCM, STT-MRAM, and RRAM (Mutlu et al., 2018).