Tunable charge-trap memory based on few-layer MoS2 (1407.7432v1)

Abstract: Charge-trap memory with high-\k dielectric materials is considered to be a promising candidate for next-generation memory devices. Ultrathin layered two-dimensional (2D) materials like graphene and MoS2 have been receiving much attention because of their novel physical properties and potential applications in electronic devices. Here, we report on a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. Owing to the extraordinary trapping ability of both electrons and holes in HfO2, the MoS2 memory device exhibits an unprecedented memory window exceeding 20 V. More importantly, with a back gate the window size can be effectively tuned from 15.6 to 21 V; the program/erase current ratio can reach up to 104, far beyond Si-based flash memory, which allows for multi-bit information storage. Furthermore, the device shows a high mobility of 170 cm2V-1s-1, a good endurance of hundreds of cycles and a stable retention of ~28% charge loss after 10 years which is drastically lower than ever reported MoS2 flash memory. The combination of 2D materials with traditional high-\k charge-trap gate stacks opens up an exciting field of novel nonvolatile memory devices.

• The paper introduces a dual-gate MoS2 charge-trap memory device that achieves a >20V memory window and a 10^5 program/erase current ratio.
• The device is engineered with a three-layer Al2O3/HfO2/Al2O3 stack integrated with few-layer MoS2, delivering enhanced electron and hole trapping and a field-effect mobility of 170 cm²V⁻¹s⁻¹.
• Its robust endurance and retention—exhibiting only 28% charge loss over a decade—highlight its potential for flexible, transparent, and multi-bit nonvolatile memory applications.

Charge-Trap Memory in MoS$_2$ Based Devices: Advancements and Prospects

The paper under discussion showcases the development and analysis of a dual-gate charge-trap memory device leveraging few-layer molybdenum disulfide (MoS$_2$) and high-$\kappa$ dielectric materials, particularly focusing on the integration of an Al$_2$O$_3$/HfO$_2$/Al$_2$O$_3$ charge-trap gate stack. The findings underscore a significant memory window and superior electric performance due to this particular integration.

Device Construction and Characteristics

The paper presents a methodical approach to constructing a nonvolatile memory device with a dual-gate configuration that comprises a few-layer MoS$_2$ channel. The channel is integrated with a three-dimensional charge-trap gate stack made of Al$_2$O$_3$/HfO$_2$/Al$_2$O$_3$. The device demonstrates a high memory window, surpassing 20 V, attributed to the exceptional electron and hole trapping abilities of the HfO$_2$ layer within the stack. Moreover, with appropriate back-gate modulation, the memory window is effectively adjustable from 15.6 to 21 V. Notably, the device achieves a program/erase current ratio reaching $10^5$, which far exceeds the potential of traditional silicon-based flash memory, suggesting that the device is apt for multi-bit information storage applications.

Performance Metrics

The MoS$_2$ based device shows a field-effect mobility of 170 cm$^2$V$^{-1}$s$^{-1}$, marking a notable achievement in terms of electron transport capability in 2D material-based memory devices. The endurance of the device is depicted by its ability to withstand hundreds of cycles, coupled with a stable retention rate, suffering only about 28% charge loss over a decade. These characteristics are substantially enhanced compared to previously reported MoS$_2$-based flash memory devices, which typically grapple with limited memory windows, reduced mobility, and marginal trap capabilities.

Implications and Potential Applications

The integration of high-$\kappa$ dielectrics like Al$_2$O$_3$ and HfO$_2$ augments the device's performance by reducing charge leakage and coupling crosstalk, thus enhancing scalability. This stack significantly bolsters the trapping capabilities required for the multi-functional demands of modern e-memory devices. The device demonstrates potential applicability in transparent and flexible device architectures, qualifying it for prospective use in wearable technology and other advanced computation nodes.

Future Prospects

The findings suggest a promising trajectory for further developments in the field of 2D material-based nonvolatile memory devices. Future research could focus on optimizing the gate stack thickness, exploring alternative 2D materials, and refining back-gate modulation techniques to augment performance across various parameters such as speed, durability, and energy efficiency. The outcomes of such advancements have implications across a broad spectrum of electronic applications that stretch beyond conventional computing toward ubiquitous smart device interactivity.

In summary, the paper offers an incisive examination into how layered structures like MoS$_2$ can be effectively integrated with high-$\kappa$ materials to engineer memory devices with superior performance metrics, setting the stage for further innovations in electronics and materials science.