Memory-Assisted Transistors

• Memory-assisted transistors are three-terminal devices that integrate memory mechanisms with conventional FET switching to achieve bistability and in-memory computation.
• They employ techniques such as defect/trap assisted charge storage, ferroelectric polarization, ionic migration, and floating gate methods across various material platforms like 2D TMDCs and organic semiconductors.
• These devices enable steep-slope operation, reconfigurable logic, and neuromorphic functions while addressing trade-offs in retention, endurance, and scalability for advanced computing applications.

Memory-Assisted Transistors

Memory-assisted transistors comprise a broad class of three-terminal devices in which intrinsic or engineered memory elements—such as defect-mediated charge-trapping, ferroelectric polarization, or interface-driven carrier modulation—endow the transistor with nonvolatile or volatile memory capability in addition to conventional field-effect switching. This fusion fundamentally alters the device transfer characteristics, enabling bistability or multistability, cyclic hysteresis, in-memory computation, multi-level storage, and novel steep-slope operation. Memory-assistance is realized across diverse material platforms, including 2D transition metal dichalcogenides, organic semiconductors, amorphous oxides, ferroelectrics, anti-ferroelectrics, and mechanical metamaterials, each of which introduces distinct microscopic memory mechanisms and performance trade-offs.

1. Device Architectures and Material Platforms

Memory-assisted transistor functionalities have been demonstrated in a variety of device systems:

• 2D TMDC FETs: Monolayer and few-layer MoS₂, WS₂, and black phosphorus (BP) channels on SiO₂/Si, often with CVD growth and metal contacts (Ag, Cr/Au). Memory arises via intrinsic or defect-induced traps in the semiconductor or gate oxide, or via interfacial cation migration when sodium or other ions are present (Sleziona et al., 2023, Grillo et al., 2021, Mallik, 2024, Mallik et al., 2023).
• Organic OFETs: Pentacene transistors with amino-terminated self-assembled monolayers and immobilized gold nanoparticles at the oxide/Pn interface serve as charge-trapping memory elements (0802.2633).
• Amorphous oxide semiconductors: a-IGZO channels in ultra-scaled floating-gate transistors for high-density, low-power 3D NAND and associative memory (Sun et al., 2021).
• Ferroelectric and Anti-ferroelectric FETs: Gate stacks integrating Hf₀.₅Zr₀.₅O₂ or Hf₀.₂Zr₀.₈O₂ allow for remanent polarization or antiferroelectric double-well landscapes, providing programmable threshold shifts and windowed bistability (Nazzari et al., 2024, Zhao et al., 2023, Tan et al., 2021, Zhong et al., 2022).
• Mechanical Transistors: Bistable, actuated-metamaterial devices employ temperature-encoded logic and memory, enabling non-electrical, reprogrammable logic-with-memory systems (Chen et al., 2023).

Table 1 summarizes representative stack ingredients and their core memory mechanisms:

Device System	Memory Mechanism	Layer Stack Example
MoS₂ FET	HCI/defect trapping	MoS₂/SiO₂/p⁺-Si
OFET (pentacene)	Au NP trap layer	Pn/AuNP/SAM/SiO₂/p⁺-Si
a-IGZO FG	Floating-gate charge	a-IGZO/HfO₂/TiN/p-Si
FeFET/FeSBFET	Ferroelectric polarization	HfZrO/SiNₓ/SOI
AFeFET	Double-well landscape	HfO₂/a-IGZO/HZO/SiO₂
Mechanical	Bistable actuator	CP-struct/invar/mechanical

2. Microscopic Memory Mechanisms

Memory-assistance emerges through several distinct, materials-specific mechanisms:

1. Defect-/Trap-Assisted Charge Storage: Point defects, vacancy clusters, or interfacial/border traps in gate oxides or at semiconductor interfaces accumulate charge during voltage sweeps. For MoS₂, controlled Xe³⁰⁺ irradiation generates oxide-trapping centers, with the hysteresis window (ΔV_th) scaling linearly with ion fluence. Deep charge-trapping in SiO₂ provides long τ_relaxation, yielding relaxation times further extended (minutes) compared to earlier devices (seconds) (Sleziona et al., 2023).
2. Interfacial Ionic Migration: In NaCl-CVD-grown TMDC FETs, mobile Na⁺ in SiO₂ migrates under high temperature and gate field, modulating local channel doping to realize robust, nonvolatile, and multi-level memory states. These dynamics are responsible for high-temperature anticlockwise hysteresis and multi-level conductance encoding (Mallik, 2024, Mallik et al., 2023).
3. Floating Gate/Charge Storage: Organic and inorganic memory transistors use discrete metallic (e.g., Au) nanoparticles, graphene, or a TiN floating gate to retain injected charge. This approach realizes large ΔV_th shifts, sizable memory windows, high ON/OFF ratios, and durable retention against leakage processes (0802.2633, Mukherjee et al., 2020, Sun et al., 2021).
4. Ferroelectric and Antiferroelectric Polarization: Polarization charge in ferroelectric (Hf₀.₅Zr₀.₅O₂, CuInP₂S₆) layers or antiferroelectric (Hf₀.₂Zr₀.₈O₂) stacks provides bistable, field-switchable states in which the direction and magnitude of polarization are preserved in the absence of a bias. Such configurations yield nonvolatile threshold shifts, with endurance and retention dictated by interfacial trap screening and depolarization field management (Nazzari et al., 2024, Zhao et al., 2023, Tan et al., 2021, Zhong et al., 2022).
5. Thyristive Bistability: Three-terminal silicon devices (3T-TRAM) with engineered P⁺/P/N/P/N/N⁺ doping profiles exhibit gate-controlled latching and internal carrier storage, achieving low standby currents, enhanced ON/OFF ratios, and fast nonvolatile switching (Lee et al., 2024).
6. Mechanical Bistability: Kirigami-inspired, thermomechanically actuated soft beams with snap-through buckling manifest memory by switching between two mechanically stable configurations, each corresponding to a distinct logical or memory state (Chen et al., 2023).

3. Operational Principles and Kinetics

The characteristic electrical signature of memory-assisted transistors is transfer curve hysteresis in I_D–V_GS sweeps, manifesting as reading (I_DS at V_GS=0) from different stable states programmed by prior pulses. The underlying kinetics span a range of timescales:

• Charge-trapping/detrapping: Relaxation toward I_DS steady state after program/erase pulses follows single- or bi-exponential decay, with time constants τ ranging from hundreds of seconds (Au-NP pentacene, MoS₂ HCI FET) to hours (float-gate FETs), dictated by trap depth and dielectric quality. For BP FETs, deep trap-assisted retention yields τ up to tens of minutes (Sleziona et al., 2023, 0802.2633, Grillo et al., 2021).
• Ion migration: Arrhenius kinetics for mobile Na⁺ in oxide layers results in retention (τ = τ₀ exp(E_a/k_B T)) and multi-bit storage capability at elevated temperatures (T > 350 K), with τ in excess of 10³ s (Mallik, 2024, Mallik et al., 2023).
• Ferroelectric/Antiferroelectric polarization switching: Landau-Ginzburg-Devonshire models describe double-well or multi-well free energy landscapes, with domain dynamics producing ultrafast (ns–μs) or, for anti-ferroelectric cells, leakage-free retention exceeding 10 years. Capacitance division across stack layers tunes the effective threshold-voltage separation (ΔV_th) (Tan et al., 2021, Zhong et al., 2022).

A generic threshold shift due to trapped charge or polarization is

$$\Delta V_{\text{th}} = \frac{Q_\text{trap}}{C_\text{ox}}$$

or, for stack capacitances,

$$\Delta V_{\text{th}} = -Q_p \cdot \left(\frac{1}{C_{FE}} + \frac{1}{C_{ox}}\right)$$

with $Q_p$ the polarization charge or $Q_\text{trap}$ stored charge (Zhao et al., 2023, Tan et al., 2021, 0802.2633).

4. Performance Metrics: Window, Retention, and Endurance

Memory-assisted transistors are quantified by several key metrics:

• Memory Window (ΔV_th or ΔI_DS): Ranges from several volts (Au-NP pentacene: up to 22 V (0802.2633); ReS₂/h-BN/graphene: ΔV_th ~ 38 V (Mukherjee et al., 2020); FeFETs/SBFETs: typically 0.6–1.8 V (Nazzari et al., 2024, Tan et al., 2021)), up to 20–30 V for HCI-irradiated MoS₂ (Sleziona et al., 2023).
• ON/OFF Ratio: Typically 10⁴–10⁸, with 3T-TRAM achieving ~10⁶ due to low leakage (Lee et al., 2024); a-IGZO FG FETs, >10⁸ (Sun et al., 2021); SBFETs, >10³ (Nazzari et al., 2024).
• Endurance: Ferroelectric and anti-ferroelectric FETs surpass 10⁹–10¹² cycles (Zhong et al., 2022, Tan et al., 2021); floating-gate-based and 2D systems, 10²–10⁴ cycles (Grillo et al., 2021, Mukherjee et al., 2020); mechanical transistors' endurance dictated by material fatigue (Chen et al., 2023).
• Retention: Nonvolatile memories achieve 10⁴–10⁸ s retention depending on material/trap quality; e.g., ReS₂/graphene NVM: >10⁵ s (Mukherjee et al., 2020); AFeFETs: >10 years if barrier ΔU > 1.2 eV (Zhong et al., 2022); thyristor RAM: >10⁴ s (Lee et al., 2024).
• Subthreshold Swing (SS): Classical Si FETs: ~60–70 mV/dec; memory-assisted mechanisms enable sub-thermionic swing, analytically

$$SS = \frac{k_BT\ln10}{e}\frac{1}{\eta_g - \beta\tau_m\frac{dg}{dV_g}}$$

giving SS < 60 mV/dec when memory dynamics enhance the effective gate efficiency (Silva et al., 28 Oct 2025).

5. Logic-in-Memory, Multilevel, and Neuromorphic Extensions

Memory-assisted transistors support system-level functionality extending beyond storage:

• Logic-in-Memory (LiM): Ferroelectric SBFETs, FeFETs, and reconfigurable transistors enable programmable logic (NAND/NOR/XOR), single-transistor CAM, and content-addressable Hamming distance measurement within compact arrays (Nazzari et al., 2024, Zhao et al., 2023, Sun et al., 2021).
• Multi-Level/Analog Storage: TMDC mem-transistors, floating-gate and ReS₂-FG FETs, and SBFETs allow for multilevel memory operation (4 to 65 distinct current levels; ≥6 bits per device) via amplitude- or sequence-modulated programming (Mallik, 2024, Mukherjee et al., 2020).
• Neuromorphic Synapses: WS₂ and MoS₂ mem-transistors, and SBFETs, natively emulate synaptic weight potentiation, depression, and spike-timing-dependent plasticity, supporting in-memory multiply–accumulate (MAC) operations and learning rules (ANN accuracy ~95%) (Mallik, 2024, Mallik et al., 2023, Nazzari et al., 2024).
• Mechanical and Optoelectronic Coupling: Mechanical M-Transistors achieve logic-with-memory by exploiting thermal bistability (Chen et al., 2023), while 2D heterostructures integrate light-assisted, optoelectronic memory access for future all-optical or quantum information schemes (Mukherjee et al., 2020).

6. Design Principles, Challenges, and Theoretical Foundations

The core challenge in memory-assisted transistors is optimizing the trade-off between memory window, retention, speed, and endurance, while maintaining integration compatibility and scalability:

• Charge Balance and Interface Engineering: In ferroelectric FETs, retention and endurance are limited by interfacial charge screening, depolarization fields, and charge trapping at the FE/dead-layer interface. High-κ interfacial layers and minimal thickness improve performance (Si et al., 2021, Tan et al., 2021).
• Trap Engineering: Sub-thermionic switching and hysteresic control require tailoring trap depth, density, and relaxation kinetics to maximize gate efficiency (η_eff) and memory number without sacrificing speed (τ_m–τ_T separation) (Silva et al., 28 Oct 2025).
• Material Integration and Scaling: BEOL compatibility, thermal budget control, and material composition (Zr/Hf ratio, stacking order, Na⁺/K⁺ doping) determine device stack optimization across technology nodes (Tan et al., 2021, Zhong et al., 2022, Mallik, 2024).
• System-Level Impact: In logic-in-memory arrays, memory-assisted transistors lower data shuttling, reduce power, support analog computing, and shrink cell area compared to SRAM/eDRAM/CTFET baselines (Nazzari et al., 2024, Zhong et al., 2022, Sun et al., 2021).

7. Perspectives and Future Directions

Memory-assisted transistors represent a unifying, generalizable strategy for breaking through classical device limitations and enabling next-generation architectures:

• Sub-Boltzmann Slope Electronics: By leveraging slow trapping/generation and memory dynamics, SS < 60 mV/dec has been demonstrated in theory and is observable in 2D nanotransistor experiments, pointing toward ultra-low-voltage logic (Silva et al., 28 Oct 2025).
• Reconfigurable and Polymorphic Circuits: Ferroelectric and field-assisted NVMs enable real-time reconfiguration of digital and analog logic without re-fabrication, as well as highly dense, area- and energy-efficient in-memory processors for AI, edge, and secure computing (Zhao et al., 2023, Nazzari et al., 2024).
• Mechanically and Optically-Assisted Memory: Integration with mechanical metamaterials and optically-gated heterostructures expands the functionality to harsh environments and cross-modality computation (Chen et al., 2023, Mukherjee et al., 2020).
• Integration and Array Scaling: BEOL and 3D stacking, ultra-scaled channels (<100 nm), and wafer-scale CVD processes facilitate high-density, high-endurance arrays suitable for system-on-chip integration (Zhong et al., 2022, Sun et al., 2021, Mallik, 2024).

A plausible implication is that memory-assisted transistor principles are material-agnostic and theoretically sufficient for realizing steep-slope, in-memory, and neuromorphic computing across multiple technology nodes and environments.

References:

(Sleziona et al., 2023, Grillo et al., 2021, Nazzari et al., 2024, 0802.2633, Chen et al., 2023, Mallik, 2024, Sun et al., 2021, Zhao et al., 2023, Mukherjee et al., 2020, Lee et al., 2024, Tan et al., 2021, Si et al., 2021, Mallik et al., 2023, Zhong et al., 2022, Silva et al., 28 Oct 2025)