Resistive RAM (ReRAM) Technology

• Resistive RAM (ReRAM) is a non-volatile memory technology characterized by a metal–insulator–metal stack that switches between high and low resistance states.
• It leverages engineered oxide materials and stack designs to enable forming-free operation, multilevel data storage, and analog weight updates for neuromorphic applications.
• Crossbar architectures and 3D arrays in ReRAM facilitate efficient vector–matrix multiplication, addressing challenges like sneak-path interference and device variability.

Searching arXiv for recent and foundational ReRAM papers to ground the article. Resistive RAM (ReRAM, or RRAM) is a class of non-volatile memory in which a simple metal–insulator–metal device is electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS). In oxide implementations, the switching is typically associated with nanoscale conductive-path formation and rupture, whereas in related memristive descriptions the same devices are treated as passive nonlinear resistors with state-dependent, history-dependent conductance and pinched hysteresis in the $I$–$V$ plane (Gale, 2016). Across the literature summarized here, ReRAM spans binary and multilevel storage, crossbar-based analog vector–matrix multiplication, logic-in-memory, neuromorphic updates, oscillatory associative memory, graph processing, and hardware security primitives, with materials platforms ranging from TiO$_2$, HfO$_2$, TaO$_x$, Nb$_2$O$_5$, and ZnO to metal–organic frameworks such as ZIF-8 (Pritam et al., 2022).

1. Device concept and operating states

Oxide ReRAM is usually implemented as a metal–insulator–metal stack in which a transition-metal oxide, such as HfO$_2$, TiO$_2$, Ta$_2$O$V$0, Nb$V$1O$V$2, SrTiO$V$3, ZnO, Al$V$4O$V$5, NiO, or WO$V$6, is sandwiched between top and bottom electrodes. The device normally starts in HRS and changes resistance by forming and rupturing nanoscale conductive paths inside the oxide. Many oxide devices require an initial electroforming step that locally increases defect density and creates a first filament, although forming-free operation can be obtained by pre-introducing defects or by stack engineering (Pritam et al., 2022).

After forming, SET drives the device to LRS and RESET returns it to HRS. In bipolar switching, SET and RESET require opposite polarities and are primarily associated with field-driven ion migration and redox. In unipolar switching, SET and RESET occur with the same polarity but different amplitudes, and RESET is dominated by Joule heating. The review literature places TiO$V$7, HfO$V$8, Ta$V$9O$_2$0, and Nb$_2$1O$_2$2 primarily in the valence-change class, while Ag/Cu-based conductive-bridge cells exemplify electrochemical metallization (Gale, 2016).

The memristor interpretation and the memory interpretation are closely related but not identical. The TiO$_2$3 thin-film device reported by Strukov et al. in 2008 is identified in the review literature as a memristor whose state evolves via ionic motion, whereas ReRAM is treated as the memory technology based on the same resistive switching phenomenon (Gale, 2016). This convergence matters because the same stateful conductance dynamics that support binary storage also enable analog weight updates, logic primitives, and crossbar computation.

Architecturally, ReRAM cells appear in 1R, 1T1R, 1S1R, complementary resistive switch, and monolithic 3D organizations. The 1T1R topology is used to suppress sneak paths and provide compliance during programming, while complementary resistive switches encode logic states as anti-serial combinations of two resistive elements so that both stored states remain high-resistance and passive crossbar sneak currents are suppressed (Pelke et al., 2024, Siemon et al., 2014).

2. Switching physics and transport regimes

The dominant switching mechanisms in the cited literature are filamentary conduction, interfacial barrier modulation, and metal-cation conductive bridging. In TiO$_2$4 and related oxides, the canonical physical picture is oxygen-vacancy motion and redox: vacancies drift under field, accumulate into a conductive filament, and are depleted or reoxidized during RESET. In electrochemical metallization cells, Ag or Cu oxidizes at the active electrode, drifts through the dielectric, and reduces at the counter-electrode to form a metallic bridge (Pritam et al., 2022).

Charge transport in HRS and LRS is correspondingly regime-dependent. The reviews and device papers repeatedly invoke Schottky emission, Poole–Frenkel emission, space-charge-limited current (SCLC), trap-assisted tunneling, Fowler–Nordheim tunneling, and Ohmic conduction. Representative forms appearing in the data include

$_2$5

$_2$6

and

$_2$7

with Ohmic readout often reduced to $_2$8 or $_2$9 in array form (Kaushik et al., 3 Jan 2025, Chowdhury et al., 20 Sep 2025).

Recent device studies make this regime structure explicit. In a solution-processed Al/ZIF-8/ITO device, the fitted transport path progresses from Ohmic conduction at low field, to Schottky emission, to SCLC in HRS, and finally to Ohmic LRS after filament formation. The same work segments the log–log slopes during SET as 1.11, 1.51, 2.44, and 1.01 across the identified regions, and attributes the filament to Zn-related conduction channels (Kaushik et al., 3 Jan 2025). In TaO$_2$0 crosspoint devices with controlled oxygen stoichiometry, oxygen-deficient HRS is described as Poole–Frenkel-dominated with low-voltage deviations, whereas oxygen-rich HRS exhibits low-voltage Ohmic behavior, Fowler–Nordheim tunneling from 0.3–0.625 V, and trap-assisted processes at higher voltage; LRS changes from low-bias Schottky-like conduction in oxygen-deficient films to low-bias Ohmic behavior in oxygen-rich films (Chowdhury et al., 20 Sep 2025).

HfO$_2$1-based studies sharpen the defect picture further. For Si/TaN/HfO$_2$2/Ni structures, HRS transport is quantitatively fitted by phonon-assisted multiphonon tunneling between traps, with the traps identified as oxygen vacancies. The extracted thermal trap energy is $_2$3 eV and the optical trap energy is $_2$4 eV, while LRS is better described not as a pure metallic filament but as a percolative pathway through nonstoichiometric HfO$_2$5 with fluctuation amplitude $_2$6 eV and fluctuation length scale $_2$7–4 nm (Islamov et al., 2013). This distinction is important because it replaces the oversimplified “metal wire” picture with a defect-network description.

Forming-free HfO$_2$8 can also be realized by changing the initial defect landscape. In Pd/HfO$_2$9 devices, a Pd–O–Hf configuration lowers the barriers for charge redistribution and oxygen-vacancy reconfiguration at room temperature. Arrhenius analysis gives $_x$0 eV and $_x$1 eV for pristine Pd-based devices, smaller than in pristine Pt controls, and double-log $_x$2–$_x$3 slopes evolve from approximately 1 to approximately 1.5 to approximately 2, consistent with shallow-trap SCLC in the forming-free state (Hua et al., 28 May 2025).

3. Materials systems and stack engineering

The oxide literature emphasizes that stack design controls forming, polarity, retention, endurance, and analogity. Electrode choice is a primary lever: inert electrodes such as Pt, W, and TiN favor vacancy-mediated VCM; active electrodes such as Ag and Cu enable ECM; oxygen-reservoir electrodes or interlayers such as Ta, Ti, NbO$_x$4, and WO$_x$5 reshape local redox and can introduce self-rectification or self-compliance (Pritam et al., 2022). TiO$_x$6 is treated as the archetypal material because it readily forms oxygen-vacancy-rich sub-oxides and Magnéli phases, exhibits both filamentary and interfacial switching, and has been central to both ReRAM and memristor model development (Gale, 2016).

The data contain several instructive recent exemplars. A thermally stable metal–organic framework ReRAM based on ZIF-8 uses an Al/ZIF-8/ITO stack, where the ZIF-8 film is synthesized by room-temperature solution precipitation in methanol and then spin-coated at 2000 rpm for 30 s with a 5 min anneal at 120 $_x$7C, yielding films of about 150 nm. The devices are forming-free, bipolar, and thermally robust from $_x$8C to $_x$9C, with an on/off ratio of approximately $_2$0, retention of at least $_2$1 s, and consistent operation over 60 cycles (Kaushik et al., 3 Jan 2025).

A distinct HfO$_2$2 route is the forming-free Pd/Ti/HfO$_2$3/Ti/Pd stack. The reported device uses 5 nm Ti and 50 nm Pd electrodes around a nominal 5 nm HfO$_2$4 layer, shows $_2$5 V and $_2$6 V across 42 devices, supports eight stable resistance levels through RESET-stop-voltage modulation, and improves $_2$7 variability relative to Pt controls, with cycle-to-cycle variability of 7.7% and device-to-device variability of 16.8% (Hua et al., 28 May 2025). The evidence for Pd extending a few nanometers into HfO$_2$8 comes from STEM-EELS and Rutherford backscattering, while AFM rules out simple roughness-driven spike artifacts.

TaO$_2$9 also remains a major reference system. In Ti/Pt/TaO$_5$0/Ta/Pt crosspoint devices, oxygen partial pressure during sputter deposition directly changes the O/Ta ratio, the forming voltage, and the conduction mechanism mix. Oxygen-rich films require larger forming fields and show broader HRS current distributions; oxygen-deficient films form conductive filaments more readily and favor multilevel modulation by gradual filament control (Chowdhury et al., 20 Sep 2025). The practical implication, stated in the data, is that oxygen stoichiometry serves as a first-order control knob on vacancy density, ionic mobility, switching thresholds, and variability.

4. Crossbars, array architectures, and computing modalities

ReRAM crossbars implement analog vector–matrix multiplication natively through Ohm’s and Kirchhoff’s laws. In the electrical domain,

$_5$1

while in neural notation the same operation is

$_5$2

Signed weights are commonly represented by differential pairs,

$_5$3

with the sensed current proportional to $_5$4 (Maram et al., 2023). This mapping is the basis of ReRAM-based processing-in-memory for DNN training and inference, CNN acceleration, graph processing, and oscillatory neural networks.

For DNN training, CrossSim models device nonidealities through experimentally derived lookup tables and trains a 3-layer classifier on the Breast Cancer Wisconsin (Diagnostic) dataset while reproducing nonlinear, asymmetric, and stochastic conductance updates. The study compares eight device configurations spanning TaO$_5$5 ReRAM, ENODe/ECRAM, and spintronic DWMTJ devices, with training accuracy exceeding 92% in all cases and reaching 97.8% for DWMTJ SOT at 400 K (Maram et al., 2023). The specific value of this work is not a new device, but a device-aware accelerator model in which analog MACs are performed in memory while gradient updates are mapped back into realistic, noisy conductance changes.

For inference, the literature addresses both arithmetic density and peripheral overhead. RED reorganizes deconvolution on ReRAM by decomposing each kernel into $_5$6 sub-crossbars and combining pixel-wise mapping with zero-skipping dataflow. On evaluated GAN and FCN layers, this yields a 3.69$_5$7–31.15$_5$8 speedup and an 8%–88.36% energy reduction relative to a zero-padding baseline (Fan et al., 2019). ReDy instead attacks the ADC bottleneck in ISAAC-like analog accelerators by dynamically quantizing activation groups in bit-serial CNN inference. Across VGG-16, ResNet-50, and DenseNet-161, the average activation bit-width becomes 6.1 bits, crossbar and ADC activity falls by 33.8% on average, and total energy drops by 13% with less than 1% top-1 accuracy loss (Sabri et al., 2023).

Monolithic 3D ReRAM uses the intertwined structure of stacked layers to implement multi-channel convolution. In a 16-layer design, cross-layer current summation performs the superimposition step of convolution directly, while configurable interconnects separate positive and negative weights. The reported gains are 5.79$_5$9 over a custom 2D ReRAM baseline, 927.81$_2$0 over CPU, and 36.8$_2$1 over GPU, with corresponding energy reductions of 2.12$_2$2, 1802.64$_2$3, and 114.1$_2$4 (Ko et al., 2020).

Beyond neural inference, ReRAM has also been used as a general near-data arithmetic substrate. GraphR stores graph blocks in ReRAM and executes sparse matrix–vector kernels in Graph Engines, obtaining a geometric-mean speedup of 16.01$_2$5 and a 33.82$_2$6 energy saving relative to a CPU baseline, and 1.69$_2$7–2.19$_2$8 speedup with 4.77$_2$9–8.91$_2$0 lower energy than a GPU (Song et al., 2017). In logic-in-memory, complementary resistive switches support multi-bit adders directly in passive crossbars, with the proposed Precalculation and Toggle-Cell adders using $_2$1 and $_2$2 CRS cells, respectively, and requiring $_2$3 and $_2$4 cycles (Siemon et al., 2014).

A particularly recent architecture uses ReRAM as a dense, programmable coupling matrix for an oscillatory neural network. A BEOL-integrated CMO/HfO$_2$5 1T1R crossbar in a 350 nm node is wire-bonded as a 5$_2$65 array and programmed with 60 ns pulses of +1.6 V and $_2$7 V. Active couplers are set to about 2 k$_2$8, unused cells remain near 10 M$_2$9, selector gates are driven to 4.5 V during inference, and a 2$_2$02 network of 9-stage ring oscillators retrieves horizontal, vertical, and diagonal patterns at approximately 8.6 kHz within one oscillation period (Choi et al., 18 Mar 2025). This places ReRAM not merely as a storage element but as an in-memory analog coupling operator.

5. Variability, reliability, and channel abstractions

ReRAM variability is intrinsic to repeated conductive-filament formation and rupture. The data distinguish cycle-to-cycle variability, device-to-device variability, read disturb, endurance degradation, retention drift, and thermal effects, and they treat these not as peripheral nuisances but as central system constraints (Pelke et al., 2024). In HfO$_2$1-based 1T1R crossbars characterized with a fully automated NeuroBreakoutBoard control platform, increasing $_2$2 increases cycle-to-cycle dispersion for both LRS and HRS, and positive read bias in the SET direction promotes HRS drift toward LRS; negative read bias in the RESET direction is therefore the safer operating condition for the studied TiN/Ti/HfO$_2$3/TiN cells (Pelke et al., 2024).

Quantitative reliability figures vary widely by stack. The ZIF-8 device maintains distinguishable states from $_2$4C to $_2$5C, retains HRS/LRS separation for at least $_2$6 s, and endures 60 consecutive SET/RESET cycles, though exact speed and energy per event are not reported (Kaushik et al., 3 Jan 2025). PdNeuRAM extends this to endurance over $_2$7 DC cycles, retention greater than $_2$8 s, and stability under $_2$9 reads at 0.1 V, with eight stable conductance levels (Hua et al., 28 May 2025). The HfO$V$00 case study on the NeuroBreakoutBoard additionally reports that some cells fail after approximately 100 SET/RESET cycles while others preserve stable HRS after approximately $V$01 cycles, underscoring the spread in endurance even within a single oxide family (Pelke et al., 2024).

At array scale, the major pathology is sneak-path interference. In the channel model for an $V$02 crossbar, HRS cells can be corrupted by unintended parallel conduction loops, yielding an effective resistance

$V$03

with the interference affecting HRS reads but not LRS reads in the idealized asymmetric model (Song et al., 2020). Because the event indicator depends on the entire stored array and selector failures, the symbol-wise channels are correlated and data-dependent. This motivates across-array coding, real-time channel estimation, and shaping. The cited scheme uses a serial concatenation of an optimized IRA code with a rate-1 data shaper, achieving 0.542824 bits/cell for a $V$04 array at $V$05 and 0.414735 bits/cell for a $V$06 array at the same noise level, close to the stated lower-bound capacities 0.660 and 0.494, respectively (Song et al., 2020).

A related detection study formulates the quantized ReRAM channel as a lognormal-mixture discrete memoryless channel governed by the sneak-path occurrence probability $V$07. Mutual-information-maximized one-bit and multi-bit quantizers are designed as functions of $V$08, and array-level or column-level adaptive detection is driven by online $V$09 estimates. The reported result is that three-bit quantization with only one iterative detection-and-decoding step approaches ideal performance, with column-level adaptation outperforming array-level adaptation because sneak-path correlation is stronger within rows and columns than across the whole array (Li et al., 2024).

This reliability literature also suggests a methodological split. For memory operation, variability is usually something to be minimized through pulse control, filtering, and selector design. For security, the same variability can be exploited directly.

6. Security primitives and current directions

ReRAM variability, analog statefulness, and irreversible wear have been repurposed for identity, unclonability, and anti-counterfeiting. One technique embeds an irreversible watermark in commercial ReRAM by repeatedly stressing selected cells with set/reset cycling until their write times become measurably larger than those of fresh cells. In Fujitsu MB85AS8MT 8 Mb SPI ReRAM, one watermark bit is mapped to 256 consecutive addresses, imprinting proceeds at approximately 0.6 bit/min, and retrieval by timing page writes proceeds at approximately 15.625 bits/s. Using $V$10, stressed and fresh cells become clearly separable after approximately 10k stress pairs, and the separation remains robust after a 3 h bake at $V$11C (Ferdaus et al., 2022).

A stronger physically unclonable function can be built from unformed ReRAM rather than cycled devices. In an Al/Al$V$12O$V$13/W 1R1T array, the protocol reads pristine cells at currents from 105 to 793 nA, aligns chip medians to 1000 ADC counts with an analog offset, and compares cell voltages differentially across chip pairs. After enrollment filtering with a single-cell $V$14 cutoff of 30 ADC counts and a pairwise margin rule $V$15, the effective pool is approximately $V$16 pair/current options for $V$17 and $V$18 (Garrard et al., 3 Oct 2025). The resulting PUF exhibits average BER of $V$19, average intra-device Hamming distance of $V$20, uniqueness of 50.025%, diffuseness of 49.982%, and uniformity of 49.937%, with client-side power below 1 mW (Garrard et al., 3 Oct 2025).

Recent device papers also frame current ReRAM development as a search for better initial states, lower-voltage operation, and tighter control of analog conductance. The ZIF-8 MOF device is notable for combining forming-free bipolar switching, multilevel memory, and synaptic-like potentiation/depression in a low-temperature solution-processed film (Kaushik et al., 3 Jan 2025). PdNeuRAM combines forming-free HfO$V$21, eight stable resistance levels, and system-level neuromorphic energy benefits, reducing write energy by approximately 43% and read energy by approximately 73% when mapped to spiking neural networks with three multilevel devices per synapse (Hua et al., 28 May 2025). BEOL-integrated CMO/HfO$V$22 couplers show that analog ReRAM can also be deployed as an in-memory phase-coupling element rather than only as a stored weight (Choi et al., 18 Mar 2025).

A plausible implication is that the most consequential near-term distinction within ReRAM is not simply between “memory” and “compute,” but between stacks whose defect landscapes remain stochastic and fragile and stacks whose interfaces, oxygen exchange, and filament geometry are deliberately engineered for a targeted operating mode. The literature surveyed here repeatedly identifies the same frontier variables: forming-free operation, variability statistics, selector integration, multilevel stability, pulse-based neuromorphic metrics, endurance beyond current demonstrations, and scalable BEOL-compatible arrays (Kaushik et al., 3 Jan 2025, Hua et al., 28 May 2025, Choi et al., 18 Mar 2025).