Device-Circuit-Architecture Co-Design

• Device-circuit-architecture co-design is a cross-layer optimization method that jointly refines device models, circuit parameters, and system metrics.
• It systematically translates device-level nonidealities into critical metrics such as BER, latency, energy consumption, and DNN accuracy.
• Its applications span RFICs, in-memory computing, and electronic-photonic systems, emphasizing integrated, iterative design for optimal performance.

Device-circuit-architecture co-design is a cross-layer design methodology in which device physics, circuit implementations, and architectural or application-level objectives are optimized jointly rather than sequentially. In contemporary research, the approach appears in reconfigurable RFICs, in-memory computing arrays, ferroelectric memories, stochastic-memristive neural circuits, electronic-photonic integrated circuits, and domain-specific SoCs, where device- and circuit-level non-idealities are propagated upward to metrics such as BER, EVM, DNN accuracy, latency, energy, area, sense margin, and robustness under process, voltage, temperature, parasitic, and workload variation (Das et al., 2024, Wang et al., 2023, Yin et al., 2024). The same literature also shows that the boundary of the topic is porous: many recent works extend the co-design loop to algorithms, software, training, or even materials, but they retain the same central premise that local optima at one layer do not reliably translate into system optima.

1. Scope, objectives, and recurring design logic

The core objective of device-circuit-architecture co-design is to couple physical behavior to end metrics that matter at deployment. In wireless design, this means linking transistor noises, intermodulation/harmonic distortions, and memory effects from parasitic capacitances to BER, SER, EVM, MER, and PER under complex modulated packets and variable channel conditions (Das et al., 2024). In in-memory computing, it means translating non-ideal currents, IR drop, sense margin, process variation, and peripheral limitations into DNN inference accuracy, energy, and robustness (Wang et al., 2023). In electronic-photonic AI systems, it means carrying insertion loss, modulation efficiency, device bandwidth, thermal crosstalk, and layout constraints into latency, link budget, area, and workload-aware energy (Yin et al., 2024).

A recurring theme is that optimizing an isolated layer is insufficient. In the IMC-SNN literature, prior improvements at individual layers are described as insufficient in isolation, and the review emphasizes the critical need for comprehensive system-level analyses considering the inter-dependencies between algorithms, devices, circuit, and system parameters (Moitra et al., 2024). In analog design, AI-assisted transistor sizing and AI-integrated circuit transfer function modeling are presented explicitly as a path from device-level tuning to system-level co-optimization (Hu et al., 17 Apr 2025). In CiM neural accelerators, NACIM broadens exploration from neural architecture alone to device type, circuit topology, quantization, and variation-aware evaluation (Jiang et al., 2019).

This perspective also corrects a common misconception: better device metrics do not automatically imply better system behavior. The synaptic-crossbar study shows that compactness and high ON/OFF current ratio matter because they reduce wire resistance and improve robustness at the array level, not merely because they improve an isolated device figure of merit (Wang et al., 2023). The IMC-SNN review makes the same point in a different form by noting that higher conductance precision can reduce the required number of crossbars but can also necessitate higher-resolution ADCs, which increase area and energy at the periphery; the review therefore argues against blindly maximizing device precision (Moitra et al., 2024).

2. Formal foundations and problem formulations

A rigorous mathematical foundation is provided by Andrea Censi’s theory of co-design, which defines a design problem through a functionality space $F$, an implementation space $J$, a resources space $R$, and feasibility relations induced by $\mathrm{exec}: J \to F$ and $\mathrm{eval}: J \to R$. For a required functionality $f \in F$, the minimal resources are expressed as

$$h(f) := \mathrm{Min} \{ \mathrm{eval}(i) \;|\; i \in J, f \leq \mathrm{exec}(i) \} \subseteq R.$$

Because resources are partially ordered, the solution is an antichain rather than a single scalar optimum, and recursive interdependencies are handled through least fixed points computed by Kleene’s algorithm in the class of Monotone Co-Design Problems (MCDPs) (Censi, 2015). This framework is notable because it treats co-design as inherently multi-objective, nonconvex, nondifferentiable, and sometimes discrete or discontinuous.

A second formal strand emphasizes bound design spaces and explicit interdependencies. In many-core co-design automation, the Application Complexity Design Space, Heterogeneous Many-Core Architecture Design Space, Parallel Programming Language Design Space, Simulator Design Space, and Optimizer Design Space are treated as a single ensemble of “many-core co-design spaces” connected by a binding process (Dhanasekar et al., 2018). The same paper uses weighted directed graphs and hypergraphs to encode computation, communication, control flow, and locality, and defines communication complexity through

$d_{pq} = |i - k|, \qquad e_{pq} = d_{pq} D_{pq},$

with additional quantitative models for fan-in, fan-out, and surge generation (Dhanasekar et al., 2018).

A third formalization appears in search-based cross-layer optimization. NACIM combines neural architecture search with hardware-aware parameters down to device level, and uses a reward

$$R(\alpha, \beta) = \beta \times \text{accuracy} + (1-\beta) \times f(\text{latency}, \text{energy}, \text{area}),$$

while training and evaluating candidate architectures under device variation (Jiang et al., 2019). The importance of this formulation is not the particular search engine alone, but the explicit statement that the design variable is the Cartesian product of architecture, quantization, device, and circuit parameters.

Together, these formulations show that device-circuit-architecture co-design is not merely “joint tuning.” It is a family of constrained optimization problems in which feasibility, robustness, and Pareto trade-offs must be expressed across heterogeneous abstractions.

3. Cross-layer modeling, simulation, and verification workflows

In practice, co-design depends on simulation flows that preserve physical fidelity while remaining tractable for exploration. The wireless framework for self-adaptive IoT receivers is a clear example: a wireless channel simulator generates arbitrary, complex, modulated signal packets under variable channel conditions; these waveforms are transferred to a circuit simulator; transistor-level netlists and behavioral models capture noises, distortion, and memory effects; the output is demodulated; and system-level metrics are compared against the ground truth to tune circuit parameters such as LNA bias current (Das et al., 2024). The paper characterizes this as a closed-loop, cross-layer optimization from system-level simulation to circuit-level modeling to metric extraction and back to circuit adjustment.

A similar but broader philosophy underlies SimPhony, which provides a generic, extensible hardware topology representation, optics-specific dataflow modeling, data-aware energy modeling, layout-aware area estimation, link budget analysis, bandwidth-adaptive memory modeling, and seamless integration with model training frameworks for heterogeneous electronic-photonic AI systems (Yin et al., 2024). Netlists are mapped to weighted directed acyclic graphs so that insertion loss, critical path extraction, laser power, and area can be computed consistently at system scale. The total layer latency is modeled as

$$\tau_{tot} = \tau_{\text{load-input/weight}} + \tau_{\text{write-out}} + I (\tau_{\text{comp}} + \tau_{\text{reconfig}}),$$

which makes device range restrictions and reconfiguration penalties visible at architectural level (Yin et al., 2024).

Other infrastructures target adjacent layers of the same problem. The Linux-based emulation framework for domain-specific SoCs provides a user-space, POSIX-threaded runtime for accelerator integration, resource management, scheduling policy evaluation, and DAG-based application injection before silicon fabrication (Mack et al., 2020). Ark provides a programming language, validator, and dynamical system compiler for “specialized reconfigurable circuits for analog compute paradigms,” enabling progressive incorporation of analog behaviors and evaluation of nonidealities during co-design (Wang et al., 2023). These works differ in abstraction, but all treat co-design as a verification problem as much as an optimization problem.

Domain or framework	Cross-layer mechanism	Reported result
Reconfigurable wireless RX (Das et al., 2024)	System-level wireless models linked to transistor-level and behavioral RFIC models	LNA power consumption can be reduced up to 16x
AFMTJ memory interface (Choudhary et al., 12 Feb 2026)	Calibrated SPICE AFMTJ model with asymmetric pulse driver and self-timed sense amplifier	Write latency = 283 ps at 0.7 V; write energy = 38 fJ
SCATTER photonic accelerator (Yin et al., 2024)	In-situ light redistribution, power gating, and power-aware dynamic sparse training	511X area reduction and 12.4X power saving
NACIM CiM accelerator search (Jiang et al., 2019)	Joint exploration of device, circuit, and architecture under variation	0.45% accuracy loss; up to 16.3 TOPs/W

The significance of these workflows is that they replace abstract “hardware awareness” with explicit physical propagation. A plausible implication is that the value of a co-design framework depends less on whether it is labeled circuit-, system-, or architecture-level than on whether it maintains faithful bidirectional coupling across levels.

4. Memory technologies and in-memory computing

Memory-centric co-design is one of the most developed areas of the field. In synaptic crossbar arrays at the 7nm node, the comparative study of 8T SRAMs, FeFETs, ReRAMs, and SOT-MRAMs uses a custom cross-layer simulation flow grounded in physics-based device models, parasitic interconnects, and circuit-level SPICE simulations (Wang et al., 2023). Two key robustness metrics are the Non-Ideality Factor,

$J$0

and the Sense Margin,

$J$1

which are then carried into ResNet-20 inference on CIFAR-10 (Wang et al., 2023). The study reports that gate-input topology reduces non-ideality and improves robustness across all technologies; that $J$2 is the chosen tradeoff for 8T-SRAM, FeFET, and ReRAM; and that FeFET arrays deliver the highest DNN accuracy and strongest robustness to random variations because of compact layouts and high ON/OFF current ratio (Wang et al., 2023).

The same logic becomes more specialized in AFMTJ memories. Because AFMTJs combine picosecond switching with low TMR, conventional MRAM interfaces are reported as unreliable. The proposed device-circuit co-designed interface therefore uses a calibrated SPICE AFMTJ model, an asymmetric pulse driver for deterministic picosecond switching, and a self-timed sense amplifier with programmable offset, dynamic reference tracking, thermal-aware tail bias, and body-bias modulation (Choudhary et al., 12 Feb 2026). Under detailed HSPICE and SPICE co-simulations and 3.15-million sample Monte Carlo analyses, the reported figures include write latency $J$3 ps at $J$4 V, write energy $J$5 fJ, read energy $J$6 fJ for STSA+ at TT @ $J$7C and $J$8V, and BER/WER $J$9 across all evaluated corners (Choudhary et al., 12 Feb 2026). Here the architectural implication is explicit: the co-designed interface preserves AFMTJ latency and energy benefits at array level rather than allowing them to be erased by peripheral circuitry.

Variation-aware search adds a further architectural layer. NACIM reports that a state-of-the-art NAS without consideration of variation experiences accuracy degradation from $R$0 to $R$1 under device variation, whereas the variation-aware framework limits the loss to $R$2 and achieves energy efficiency up to $R$3 TOPs/W (Jiang et al., 2019). This result is notable because it treats device variation not as a post-layout nuisance but as a primary search constraint.

Taken together, these studies make a broader point: in memory-centric accelerators, the decisive bottlenecks often sit at interfaces, interconnects, and sensing margins. Device superiority is therefore inseparable from circuit topology and array organization.

5. RF, analog, and ferroelectric device-to-circuit flows

In RFIC design, co-design appears as a direct coupling between communication metrics and transistor-level tuning. The wireless framework for the Internet of Self-Adaptive Things links a reconfigurable CMOS LNA, a behavioral I/Q mixer, and ideal low-pass filters to wireless channel and baseband simulations that include multipath, fading, path loss, SNR variation, and AWGN (Das et al., 2024). The LNA bias current is tunable from $R$4 to $R$5, changing gain, IIP3, noise figure, and power consumption, and the case study reports that power consumption can be reduced by up to 16x while still meeting required BER/EVM targets for specific scenarios (Das et al., 2024). This directly challenges the worst-case-only RFIC methodology described in the same paper.

AI-driven analog design extends the same principle to optimization engines. In the transconductor case study, Multi-Objective Bayesian Optimization is used to optimize transistor sizes and operating voltages against tunable $R$6 range, $R$7 linearity, bandwidth, power consumption, and input referred noise, with a Gaussian Process surrogate and qEHVI acquisition function (Hu et al., 17 Apr 2025). The reported optimization converges in 35 trials, reduces IRN by 24%, and increases the tunable linear $R$8 range by 102% compared to baseline (Hu et al., 17 Apr 2025). At system level, the same paper embeds SPICE-accurate bandpass-filter transfer functions in a keyword spotting training loop so that classifier accuracy, power proxy, and area proxy are optimized together (Hu et al., 17 Apr 2025).

Ferroelectric research pushes the co-design boundary downward into materials. The dynamic-field-driven nucleation and growth model is introduced because standard KAI and NLS frameworks assume constant electric field and therefore fail under arbitrary, time-varying, and distorted voltage waveforms (Liang et al., 3 Feb 2026). The DFNG formulation writes the switched fraction as

$R$9

with

$\mathrm{exec}: J \to F$0

so that the full voltage history enters switching kinetics (Liang et al., 3 Feb 2026). The paper explicitly links extracted parameters to memory window, disturb error, speed, and energy dissipation, and therefore describes its method as a predictive materials-circuit co-design framework (Liang et al., 3 Feb 2026).

A closely related circuit-facing example is the defect-aware compact model for ferroelectric nvCap memories. The model combines experiments, TCAD, and VerilogA compact modeling to capture small-signal capacitance, interface and bulk defect contributions, variations, and cycling degradation, and then uses circuit-level Monte Carlo analysis for read-out optimization and endurance assessment (Fehlings et al., 26 Nov 2025). The paper reports optimized memory read-out with $\mathrm{exec}: J \to F$1 mV sense margin and frames the result as enabling selector-less arrays and 3D-stacked memories for compute-in-memory and storage memory (Fehlings et al., 26 Nov 2025).

These examples show that device-circuit-architecture co-design is not restricted to choosing device parameters and sizing transistors. In some domains, the operative cross-layer boundary begins at waveform-dependent switching physics and ends at sense-amplifier margin or application error rate.

6. Photonic systems, heterogeneous AI hardware, and automation

Photonic computing has driven some of the most explicit device-circuit-architecture formulations. SCATTER is presented as an algorithm-circuit co-sparse photonic accelerator that also requires “cross-layer device-circuit-architecture-algorithm co-optimization aware of hardware non-ideality and power bottleneck” (Yin et al., 2024). Its key hardware mechanism is an in-situ tunable rerouter built from a tree of MZI power splitters that directs light only to unpruned channels, combined with input gating, output gating, and weight MZI gating (Yin et al., 2024). The paper reports a 511X area reduction and 12.4X power saving, together with superior crosstalk tolerance that enables $\mathrm{exec}: J \to F$2 spacing and improved on-chip power efficiency (Yin et al., 2024).

SimPhony generalizes this into a reusable simulation stack for heterogeneous EPIC AI systems. Its device library, hierarchical netlists, weighted DAGs, optics-specific dataflows, memory hierarchy, and training integration support heterogeneous multi-core architectures with diverse photonic tensor core designs (Yin et al., 2024). The laser power requirement is modeled as

$\mathrm{exec}: J \to F$3

so photodetector sensitivity, insertion loss, bitwidth, wall-plug efficiency, and extinction ratio become system-visible variables rather than device-only parameters (Yin et al., 2024).

The open-source AI-infused electronic-photonic design automation stack extends this idea further by coupling SimPhony with AI-based Maxwell solvers, fabrication-aware inverse design, and scalable inverse training for meta-optical neural networks (Zhou et al., 31 Dec 2025). Reported components include NeurOLight, PACE, PIC$\mathrm{exec}: J \to F$4O-Sim, MAPS, and SP$\mathrm{exec}: J \to F$5RINT, and the case studies include Lightening-Transformer, TeMPO, SCATTER, and meta-optical neural networks (Zhou et al., 31 Dec 2025). The practical significance is that device simulation, circuit abstraction, and system exploration can be accelerated and differentiated enough to support repeated cross-layer iteration rather than one-off analysis.

Adjacent work on deployment-aware neural design shows how the topic continues to broaden. GCoDE co-designs GNN architecture search and operation mapping on device-edge hierarchies by abstracting communication as an explicit operation and jointly optimizing accuracy, latency, and on-device energy under constraints (Zhou et al., 2024). Although the paper is framed around device-edge co-inference rather than circuit layout, it preserves the central co-design pattern: a unified design space, performance-aware predictors, and runtime adaptation through an architecture zoo and dispatcher (Zhou et al., 2024).

A plausible implication of these photonic and AI-infused flows is that future device-circuit-architecture co-design will increasingly be toolchain-centric. The open-source character of SimPhony and the EPDA stack, the planned use of machine learning or deep reinforcement learning agents for adaptive RFIC tuning, and the continuing integration of training loops with hardware models all point toward co-design environments in which exploration, verification, and deployment are no longer separated stages (Yin et al., 2024, Das et al., 2024, Zhou et al., 31 Dec 2025).