SPICE-Q Simulation in Quantum EDA

• SPICE-Q Simulation is a design paradigm that extends conventional SPICE to model quantum and quantum-adjacent devices using mixed-physics and co-simulation techniques.
• It employs reduction strategies by mapping complex physical device models into circuit representations that capture key metrics like qubit frequencies, anharmonicity, and decoherence.
• The framework integrates closed-loop calibration, automated tool orchestration, and version-controlled model cards to ensure traceability and yield optimization in quantum electronic design automation.

Searching arXiv for papers explicitly using or contextualizing “SPICE-Q”. SPICE-Q Simulation denotes a SPICE-inspired family of simulation methodologies in which conventional circuit simulation is extended, adapted, or embedded within workflows for non-classical devices, quantum-adjacent hardware, or large-scale model-driven design. In the most explicit sense, the term is defined in the quantum-chip literature as a unified simulation layer within Quantum Electronic Design Automation that links physical device models, quantization, packaging parasitics, and measurement feedback into an executable engineering flow for superconducting quantum chips (Cai et al., 16 Jun 2026). In a broader and more heterogeneous usage, the label also encompasses SPICE-based co-simulation of quantum charge sensors with CMOS, classical surrogate simulation of superconducting readout networks, and related mixed-physics or mixed-abstraction workflows in which SPICE remains the organizing computational substrate rather than a standalone analog circuit engine (Tanamoto et al., 2021, Tanamoto et al., 27 Jul 2025). The literature therefore uses “SPICE-Q Simulation” both as a specific framework name and as a descriptive umbrella for SPICE-centered simulation of quantum or quantum-adjacent systems.

1. Terminological scope and historical emergence

The term is not uniform across the literature. The 2026 “Quantum Chip Paradigm Framework” defines SPICE-Q as “the quantum-circuit counterpart of classical SPICE” and places it at the core of Q-EDA 1.0, where it couples Josephson-junction nonlinearity, circuit quantization, open quantum dynamics, packaging electromagnetic models, and measurement feedback (Cai et al., 16 Jun 2026). A closely related 2026 work on large-scale superconducting quantum-chip production characterizes SPICE-Q as a “SPICE-inspired, DTCO framework” that stitches together parametric layout, full-wave electromagnetics, energy-participation-ratio extraction, Hamiltonian modeling, open-system noise, and manufacturing statistics into a single versioned model chain (Cai et al., 16 Jun 2026).

Other papers use the expression more loosely. The 2021 study of paired single-electron-transistor and CMOS readout explicitly states that it does not define a specific SPICE-Q framework, but identifies its own SmartSpice-plus-Verilog-A methodology as “precisely what ‘SPICE-Q’ would imply” for quantum charge-sensing co-simulation (Tanamoto et al., 2021). The 2025 superconducting-readout paper uses conventional SPICE to model large readout arrays with linearized LCR surrogates and presents this as a practical SPICE-Q methodology for early-stage fidelity screening at scales up to 10,000 qubits (Tanamoto et al., 27 Jul 2025). This suggests that SPICE-Q is not a single solver family but a design pattern in which SPICE-compatible abstractions are used to bridge device physics, circuit behavior, and system-level engineering.

A persistent misconception is that SPICE-Q names one monolithic simulator. The available papers instead describe a layered ecosystem. In the superconducting-chip literature, SPICE-Q explicitly does not replace tools such as HFSS, Qiskit Metal, pyEPR, SQcircuit, scqubits, SQuADDS, or QuTiP; it connects them through standardized interfaces and versioned model cards (Cai et al., 16 Jun 2026). In the SET/CMOS and spin-qubit readout literature, SPICE-Q-like workflows similarly depend on external device-level solvers such as TCAD, with SPICE handling compact or behavioral circuit integration rather than full microscopic physics (Tanamoto et al., 2021, Tanamoto et al., 9 Dec 2025).

2. Core modeling principle: extending SPICE beyond conventional compact models

Across its variants, SPICE-Q Simulation is organized around the idea that physically rich or nonstandard devices can be represented in circuit form strongly enough to preserve the engineering questions of interest. In superconducting Q-EDA, this means that layout-derived physical structures are mapped to circuit graphs with generalized flux and charge variables, then reduced through quantization and open-system dynamics into metrics such as qubit frequency, anharmonicity, coupling, dispersive shift, decoherence, and yield (Cai et al., 16 Jun 2026). In the DTCO-oriented formulation, the model chain is explicitly stated as: process and PDK constraints to parametric layout, to electromagnetic simulation, to energy participation and equivalent $C/L/Z(\omega), S$, to circuit quantization, to effective Hamiltonians, and finally to performance and yield metrics (Cai et al., 16 Jun 2026).

In hybrid charge-sensing readout, the same principle appears in a more classical form. SETs are represented in SPICE using Verilog-A subcircuits derived from orthodox single-charge-tunneling theory, while CMOS is modeled with BSIM4; the resulting simulator captures the full two-stage readout chain from picoamp Coulomb-oscillation currents to latched CMOS outputs (Tanamoto et al., 2021). In silicon spin-qubit readout, TCAD first computes state-dependent GAA transistor $I$–$V$ characteristics under different charge distributions, and those characteristics are then embedded into SmartSpice as Verilog-A behavioral models inside a multi-stage sense chain (Tanamoto et al., 9 Dec 2025). In large superconducting-readout arrays, the Josephson device is not modeled directly; instead, the transmon is replaced by an LCR surrogate chosen to reproduce target $\omega_q$ and $T_1$, allowing standard SPICE to evaluate spectral crowding and variation sensitivity at large scale (Tanamoto et al., 27 Jul 2025).

A plausible implication is that SPICE-Q should be understood less by its syntax than by its reduction strategy. The common pattern is the use of physically derived compact, behavioral, or surrogate elements that preserve the dominant interactions needed for a given design task while deferring full microscopic treatment to upstream solvers or calibration loops.

3. Superconducting quantum-chip SPICE-Q

In the explicit Q-EDA definition, SPICE-Q is centered on superconducting hardware and begins from physical structures rather than HDL-like abstractions. The cited framework argues that superconducting quantum systems are governed by microwave physics, open-system noise, and packaging sensitivity, so qubit frequencies, anharmonicity, coupling, and readout must be derived from device geometry, materials, and 3D environment (Cai et al., 16 Jun 2026). Its device-level equations therefore include the DC Josephson relation $I(\phi)=I_c\sin\varphi$, the AC Josephson relation $V=\frac{\Phi_0}{2\pi}\frac{d\varphi}{dt}$, the RCSJ branch equation, the transmon Hamiltonian $H=4E_C(n-n_g)^2-E_J\cos\varphi$, and the Lindblad master equation for decoherence (Cai et al., 16 Jun 2026).

The solver architecture is correspondingly mixed. The classical nonlinear core uses modified nodal analysis with Newton-Raphson for Josephson nonlinearity in transient and harmonic-balance settings, while the quantum core uses master-equation integration for reduced Hilbert spaces, sparse Liouvillian methods, and time-dependent Hamiltonian integration for control pulses (Cai et al., 16 Jun 2026). Frequency-domain integration is handled through admittance or S-parameter ingestion from package and interconnect models, which are stitched into the circuit and linearized around operating points to plan readout and coupling windows (Cai et al., 16 Jun 2026). The DTCO-oriented companion work emphasizes the same structure but rephrases it as a standardized chain joining parametric layout, EM extraction, EPR compression, circuit quantization, noise modeling, and Monte Carlo yield analysis under version governance (Cai et al., 16 Jun 2026).

The following table condenses the main functional blocks of superconducting SPICE-Q as presented in the two 2026 papers.

Layer	Inputs	Outputs
Physical and PDK	Layer stack, material data, JJ distributions, DRC/LVS rules	Versioned model cards, PCells, statistical corners
EM and reduction	Layout, ports, package boundaries	$S_{ij}(\omega)$, $Z(\omega)$, mode fields, EPR tables
Circuit and quantum model	JJ parameters, reduced linear network	$I$0, $I$1, $I$2, $I$3, $I$4, $I$5 estimates
DTMO and yield	Fabrication data, cryogenic measurement, process distributions	Calibrated model updates, sensitivity maps, yield predictions

A central feature is closed-loop calibration. Fabrication distributions for $I$6, dielectric loss, thickness, or coupling parasitics and cryogenic measurements of frequency, $I$7, $I$8, or $I$9 are fed back to update model cards and participation factors (Cai et al., 16 Jun 2026, Cai et al., 16 Jun 2026). This is presented as essential for moving from isolated simulations to auditable engineering objects. The emphasis on provenance is unusually strong: layouts, EM decks, EPR tables, Hamiltonians, measurement datasets, and analysis manifests are all treated as versioned artifacts with unit-system tracking and traceable transformations (Cai et al., 16 Jun 2026).

4. Hybrid quantum-classical readout and co-simulation

A second major SPICE-Q lineage concerns readout circuits where quantum or quantum-adjacent sensors are embedded into conventional electronics. The 2021 SET/CMOS work is exemplary. Its goal is to read out tiny charge-induced current changes from SETs using CMOS-compatible circuits by amplifying the difference between two SETs—a target and a reference—rather than a single SET (Tanamoto et al., 2021). The first amplification stage directly series-connects each SET to a pMOS transistor, converting sub-picoamp Coulomb-oscillation currents into a few-millivolt voltage signal; the second stage performs differential amplification using CMOS circuits such as a differential amplifier, 6T SRAM cell, DRAM-like sense amplifier, or cross-coupled pair (Tanamoto et al., 2021). The reference SET provides baseline cancellation, suppressing common-mode variations including threshold mismatch, slow drift, and temperature-induced offsets (Tanamoto et al., 2021).

SET device behavior is encoded via Verilog-A subcircuits using orthodox single-charge-tunneling theory, with parameters $V$0 and charging energy $V$1 (Tanamoto et al., 2021). CMOS uses BSIM4 device models in SmartSpice. Under low-temperature SET conditions and conventional CMOS parameters, the first stage converts Coulomb oscillations to about 10 mV peak-to-trough in $V$2, and the second-stage differential amplifier can produce output differences of about 40 mV (Tanamoto et al., 2021). A 300-run Monte Carlo with $V$3 threshold variation on CMOS transistors found only 9 samples with small differential amplitudes below 5 mV, which the authors interpret as strong resilience to threshold variations (Tanamoto et al., 2021). This is a canonical SPICE-Q example in the sense that nonstandard charge-sensing physics is reduced to a SPICE-compatible device model and then propagated through digital-compatible latching circuits.

The 2025 silicon spin-qubit/GAA-transistor study follows a parallel structure. Logical qubit states produce different charge distributions in neighboring quantum dots, which alter the electrostatics and current of a nearby gate-all-around transistor (Tanamoto et al., 9 Dec 2025). Silvaco Atlas TCAD computes state-dependent transistor characteristics under those charge configurations, and SmartSpice then evaluates a three-stage CMOS sense chain plus SRAM-type latch, with the GAA injected as a behavioral source based on TCAD-derived $V$4 tables (Tanamoto et al., 9 Dec 2025). The paper reports robust logical-state ordering in the GAA current, $V$5, and demonstrates that a dynamic wordline waveform can keep qubit-facing nodes at low current while still resolving the final latch to digital rails (Tanamoto et al., 9 Dec 2025). This suggests a broader SPICE-Q pattern in which device-level quantum-state dependence is projected into compact circuit observables suitable for standard sensing architectures.

The 2025 large-scale superconducting-readout paper extends the same philosophy to array-level modeling. Each qubit-resonator cell is reduced to passive LCR elements, with $V$6 encoding $V$7 and coupling capacitors encoding interconnect or readout structure (Tanamoto et al., 27 Jul 2025). Although the Josephson nonlinearity and explicit dispersive shift $V$8 are not simulated, the method enables AC-sweep screening of frequency collisions and readout topology sensitivity under Gaussian parameter spreads, including system sizes up to 10,000 qubits on a laptop (Tanamoto et al., 27 Jul 2025). The “fidelity” reported there is not a single-shot measurement fidelity, but a circuit-level proxy derived from $V$9, $\omega_q$0, and an operation time parameter (Tanamoto et al., 27 Jul 2025). This is important because it clarifies that SPICE-Q can serve at very different abstraction levels, from pulse-level or switching-level waveform prediction to coarse architectural risk estimation.

5. Mixed-physics formulations beyond qubit readout

SPICE-Q-like methodologies also appear in other nonstandard circuits where classical SPICE is coupled to physics not usually handled by compact IC models. In stochastic ReRAM and probabilistic memristor networks, the relevant dynamics are not deterministic state equations but master equations over discrete device or network states. Both “Analytic and SPICE modeling of stochastic ReRAM circuits” and “Modeling networks of probabilistic memristors in SPICE” implement occupation probabilities as voltages on 1 F capacitors and use behavioral current sources to encode the master equation directly in SPICE (Dowling et al., 2022, Dowling et al., 2020). For a binary memristor, the state probability obeys

$\omega_q$1

and the mean conductance follows from probability weighting (Dowling et al., 2022). For networks, full configuration probabilities or symmetry-reduced aggregates are evolved via coupled ODEs, enabling ensemble-average behavior without Monte Carlo trajectory simulation (Dowling et al., 2020). This is not quantum simulation in the strict sense, but it matches the SPICE-Q pattern of embedding nonstandard stochastic physics into a SPICE-compatible dynamical system.

The 2025 DC-coupled resistive silicon detector work provides a different mixed-mode example. TCAD is used to extract device-physics quantities such as sheet resistance $\omega_q$2, capacitance per unit area $\omega_q$3, junction capacitances, contact resistances, avalanche gain, and current waveforms for representative detector cells; those quantities are then mapped into a 2D RC mesh in SPICE (Croci et al., 22 Aug 2025). Signal spreading on the resistive sheet is governed by

$\omega_q$4

which is discretized via resistive links and node capacitors (Croci et al., 22 Aug 2025). The SPICE model then evaluates timing and charge-sharing behavior over lateral scales too large for efficient full-3D TCAD (Croci et al., 22 Aug 2025). Here, SPICE-Q functions as a bridge between semiconductor transport simulation and readout-circuit-level transient evaluation.

A still different usage appears in the quantum-diamond-microscope study of a 555 timer. There, transistor-level PSPICE currents are converted into current-density fields in a finite-element model, and the predicted magnetic field maps are registered against experimentally measured NV-center magnetic images (Kehayias et al., 2021). The pipeline integrates SPICE, finite-element field solving, and quantum sensing, and the paper explicitly presents it as a SPICE–QDM or SPICE-Q workflow (Kehayias et al., 2021). This suggests that the term can also designate SPICE-based coupling to quantum measurement modalities, not only to quantum devices themselves.

6. Automation, benchmarking, and software infrastructure

Recent work extends SPICE-Q ideas from physics modeling to automation and tool orchestration. “SPICEPilot” introduces a Python-based dataset and framework built around PySpice with an ngspice backend, aimed at improving LLM generation of SPICE code through structured prompting, validation, unit normalization, device-model checking, topology checks, and standardized metrics such as syntax validity, simulation success, topology correctness, directive correctness, and waveform similarity (Vungarala et al., 2024). The paper explicitly frames its methods as applicable to SPICE-Q Simulation by emphasizing explicit analysis intent, valid model libraries, topology constraints, and automated acceptance gates (Vungarala et al., 2024). Although SPICEPilot is not a physics simulator for quantum hardware, it contributes an infrastructural layer: reliable generation and validation of SPICE testbenches that could front-end SPICE-Q workflows.

“SPICEAssistant” does something analogous for switched-mode power supplies. It wraps LTSpice with tool functions that compute steady-state mean output voltage, ripple, switching frequency, and settling time, and lets an LLM iteratively modify netlists based on simulation feedback (Nau et al., 14 Jul 2025). The paper notes that “SPICE-Q” does not explicitly appear in its text, but presents a concrete interpretation of SPICE-Q as Q-factor-oriented SPICE analysis layered on top of LTSpice AC sweeps (Nau et al., 14 Jul 2025). The significance here is methodological: SPICE-Q need not imply a new solver kernel, but can also mean a structured control layer around established SPICE engines, where metrics, guardrails, and iterative refinement are automated.

A plausible implication is that future SPICE-Q systems may be as much about orchestration and provenance as about numerical kernels. This is already explicit in the superconducting DTCO literature, where model-card versioning, toolchain provenance, and cross-domain traceability are treated as core functionality rather than auxiliary documentation (Cai et al., 16 Jun 2026).

7. Limitations, controversies, and open directions

The most important limitation is model fidelity. In several SPICE-Q variants, the nonclassical device is represented only approximately. The large-scale superconducting-readout study deliberately avoids explicit Josephson nonlinearity and state-dependent dispersive pull, replacing the qubit with an LCR branch that reproduces target $\omega_q$5 and $\omega_q$6 but not full quantum behavior (Tanamoto et al., 27 Jul 2025). The SET/CMOS study models SET transport with orthodox theory but omits explicit noise spectra and cryogenic CMOS parameter extraction at 4.2 K (Tanamoto et al., 2021). The spin-qubit/GAA study runs TCAD at room temperature and SPICE at 10 K, neglects tunneling between dots and channel, and does not model measurement-induced dephasing or explicit noise (Tanamoto et al., 9 Dec 2025). These are not incidental omissions; they define the scope of what each SPICE-Q workflow can claim.

A second limitation is abstraction mismatch. Superconducting SPICE-Q papers stress that one cannot simply transplant classical HDL-first methodology into quantum-chip design because logical function is inseparable from microwave structure, materials, and package modes (Cai et al., 16 Jun 2026). Conversely, surrogate-heavy approaches may scale well but risk discarding exactly those effects—nonlinearity, state dependence, decoherence channels, or packaging resonances—that dominate system performance. The literature therefore presents a tension between scalability and physical completeness rather than a settled recipe.

A third limitation is numerical and workflow complexity. Mixed solvers combining MNA, EM extraction, quantization, Monte Carlo variability, and measurement calibration are inherently difficult to standardize. The DTCO papers address this through model cards, PCells, semantic versioning, and audit trails (Cai et al., 16 Jun 2026), while automation papers address it through prompt templates, topology validation, and standardized metrics (Vungarala et al., 2024). This suggests that the long-term evolution of SPICE-Q will depend on software engineering discipline as much as on device physics.

Future directions stated across the corpus are relatively consistent. The superconducting-chip papers call for tighter EM–quantum integration, richer Quantum PDKs, better calibration from cryogenic measurement, and agentic design loops (Cai et al., 16 Jun 2026, Cai et al., 16 Jun 2026). The SET/CMOS and spin-qubit readout papers identify cryogenic compact models, explicit noise and backaction, and automated bias calibration across arrays as unfinished tasks (Tanamoto et al., 2021, Tanamoto et al., 9 Dec 2025). The large-scale superconducting-readout paper points toward adding nonlinearity, noise, and amplifier-chain models to convert architectural screening into actual readout-SNR prediction (Tanamoto et al., 27 Jul 2025). Taken together, these works indicate that SPICE-Q Simulation is evolving from a set of ad hoc SPICE-based co-simulations into a more formalized, model-driven simulation paradigm whose defining concern is not merely solving circuits, but preserving traceability across the chain from device physics to system behavior.