Automated Circuit Discovery Methods

• Automated circuit discovery is a methodological family that replaces handcrafted designs with algorithmic search to identify compact, behaviorally faithful circuit structures.
• It employs diverse techniques—ranging from gradient descent and evolutionary algorithms to reinforcement learning—to optimize performance metrics like KL divergence and spectral fidelity.
• These methods enable faster discovery, reduced resource usage, and robust designs in applications from neural network interpretability to photonic, quantum, and analog system synthesis.

Automated circuit discovery denotes a family of methods that replace hand-designed circuit analysis or hand-crafted circuit synthesis with algorithmic search. In mechanistic interpretability, a “circuit” is a sparse, task-relevant subgraph of a model’s computational graph whose components causally implement a behavior (Conmy et al., 2023). In photonic, quantum, analog, and superconducting design, the term refers to inverse-design procedures that search over executable circuit topologies or parameterizations subject to fidelity, resource, spectral, noise, or task-performance constraints (Hartnett et al., 22 Aug 2025, Gao et al., 28 Feb 2025, Menke et al., 2019). Across these literatures, automated circuit discovery is therefore not a single algorithmic object but a shared research program: specify a target behavior, choose a representation of circuit structure, define a faithfulness or performance objective, and search for a compact or high-performing realization.

Domain	Circuit object	Representative approaches
Mechanistic interpretability	Sparse subgraph of a neural network computation graph	ACDC, EAP, PEAP, CD-T, SAE/Transcoder graphs, MechRL
Photonic and quantum design	Executable optical or quantum gate circuit	Differentiable unitary optimization, evolutionary search, PPO, GFlowNets, gadget mining
Analog and superconducting design	Topology or hardware architecture	Generative topology models, federated training, closed-loop inverse design

1. Conceptual scope and historical development

Automated circuit discovery emerged along at least two distinct lines. One line treated the problem as computational synthesis of physical circuits. A multi-objective evolutionary algorithm for quantum circuit discovery searched variable-length gate sequences “from scratch,” balancing accuracy against depth, width, gate count, and implementability, and recovered textbook constructions for the quantum Fourier transform and Grover search while also finding alternative structures (Potoček et al., 2018). SCILLA then framed superconducting-circuit design as a closed-loop inverse-design problem with proposal, property calculation, and merit evaluation modules operating asynchronously over a database-backed workflow (Menke et al., 2019). More recent work extended the same logic to photonic graph-state generation, analog integrated-circuit topology generation, and task-specific quantum-model screening (Hartnett et al., 22 Aug 2025, Gao et al., 28 Feb 2025, Innan et al., 29 Aug 2025).

The second line treated circuit discovery as mechanistic interpretability. “Towards Automated Circuit Discovery for Mechanistic Interpretability” systematized a recurring workflow: choose a behavior, dataset, and metric; choose an abstraction level and computational graph; then iteratively patch activations to isolate the relevant subgraph (Conmy et al., 2023). In that setting, the key object is not a fabricated circuit but a causally sufficient explanatory subnetwork. Later work broadened this agenda from transformer heads to token-position-specific edges, SAE features, vision-model neurons, and reinforcement-learning policies over causal interventions (Haklay et al., 7 Feb 2025, Ge et al., 2024, Rajaram et al., 2024, Khadka, 25 May 2026).

This dual usage does not collapse the distinction between explanation and synthesis. Rather, it indicates that the common denominator is algorithmic recovery of compact structure under explicit behavioral constraints. This suggests that “automated circuit discovery” is best understood as a methodological family rather than a domain-specific term.

2. Neural-network circuit discovery and mechanistic interpretability

ACDC is the canonical starting point for automated circuit discovery in transformers. The model is represented as a computational DAG, a clean dataset is paired with corrupted prompts, and edges are greedily pruned in reverse-topological order when their removal causes only a small increase in mismatch between the full model and the patched subgraph. In its main form, ACDC uses KL divergence and removes an edge when

$$D_{KL}(G \| H_{\mathrm{new}}) - D_{KL}(G \| H) < \tau.$$

On GPT-2 Small Greater-Than, ACDC rediscovered $5/5$ of the component types in a manually identified circuit and selected $68$ of the $32{,}000$ edges in the model, all of which had been manually found previously; on IOI it recovered $9$ heads, all belonging to the known IOI circuit (Conmy et al., 2023).

A central response to ACDC’s cost was Edge Attribution Patching. EAP replaces repeated activation-patching interventions with a first-order Taylor approximation:

$$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$

The method uses the absolute attribution score $\left|\Delta_e L\right|$ to rank edges, requiring only two forward passes and one backward pass. Averaged over its evaluation tasks, EAP achieved greater AUC from circuit recovery than prior methods, while remaining computationally much cheaper than repeated patching (Syed et al., 2023).

Subsequent work altered the representation of what counts as a circuit. Position-aware Edge Attribution Patching argued that prior automatic methods assume position-invariant circuits and therefore miss cross-positional interactions. PEAP differentiates token positions explicitly and introduces dataset schemas, which align variable-length prompts by ordered semantic spans rather than raw token indices. The same paper adds an automated schema-generation and schema-application pipeline using LLMs, enabling position-aware circuit discovery on IOI, Greater-Than, and Winobias with better sparsity-faithfulness trade-offs than position-agnostic baselines (Haklay et al., 7 Feb 2025).

Other lines changed the attribution mechanism itself. Contextual decomposition for transformers writes activations as $x=\beta+\gamma$, with $\beta$ the relevant contribution and $\gamma$ the irrelevant contribution, and propagates this split through self-attention and other modules. On pathology reports, CD-T reduced average runtime for building one circuit level from $5/5$0 with path patching to $5/5$1, while increasing faithfulness from $5/5$2 to $5/5$3 (Hsu et al., 2024). A more radical change came from inserting Sparse Autoencoders and Transcoders so that the model’s computation graph becomes strictly linear with respect to OV and MLP circuits for a fixed input, allowing hierarchical attribution over feature-level graphs and enabling both local and end-to-end circuit extraction in GPT-2 Small (Ge et al., 2024).

The same broad program has been extended beyond LLMs. Cross-Layer Attribution in vision models defines a functional circuit by tracing attribution between internal layers, starting from a few examples of a visual concept. CLA recovered all units in the manually discovered InceptionV1 car circuit, found additional car-selective neurons, and supported a CLIP defense against text-overlay attacks that improved adversarial traffic-light accuracy from $5/5$4 to $5/5$5 while pruning about $5/5$6 of edges in layer $5/5$7 (Rajaram et al., 2024). “Evaluating Brain-Inspired Modular Training in Automated Circuit Discovery” further argued that training regimes can change discoverability itself: BIMT, defined as L1 + Local + Swap, produced lower logit difference, faster discovery time, and higher sparsity than the compared MNIST MLP baselines (Nainani, 2024). MechRL then recast circuit discovery as a PPO problem over the $5/5$8 attention heads of GPT-2 small, using zero-ablation and a contrastive reward; a single policy trained on induction and IOI reached the per-episode oracle on both training tasks and, under best-of-five planning, recovered $5/5$9 of the oracle ceiling on held-out docstring completion (Khadka, 25 May 2026).

3. Faithfulness, evaluation granularity, and formal guarantees

A persistent issue in automated circuit discovery is whether structural differences imply mechanistic differences. “Many Circuits, One Mechanism” tested this directly by varying input statistics while holding the task fixed. Across four token-frequency bands plus control in five Pythia models, ACDC produced $68$0 circuits whose structures differed substantially, yet band-specific edges transferred broadly across bands, a universal core covering $68$1 to $68$2 of circuit nodes recurred across conditions, and a relaxed core with edges appearing in at least $68$3 of $68$4 conditions recovered at least $68$5 of full-circuit accuracy for Pythia-160M and above, with the $68$6 CI lower bound still at least $68$7 (Makou et al., 4 Jun 2026). The paper termed this pattern phantom specialization and used interchange patching plus Boundless DAS to show that the internal representations across bands were causally interchangeable, with IIA at least $68$8 for all cross-band pairs in models $68$9M.

The same work also isolated an evaluation problem. Source-level evaluation treats all outgoing edges from any selected node as clean, whereas edge-level evaluation keeps clean only the selected edges. On the universal core, source-level evaluation yielded accuracy of $32{,}000$0 to $32{,}000$1, compared with $32{,}000$2 to $32{,}000$3 at edge level, inflating apparent faithfulness by $32{,}000$4 to $32{,}000$5 accuracy points (Makou et al., 4 Jun 2026). This is directly relevant to claims of minimal circuits, because it shows that permissive evaluation can collapse an equivalence class of edge patterns into an overly coarse macro-state.

Another strand asked whether the discovered circuit can be certified beyond finite samples. “Formal Mechanistic Interpretability: Automated Circuit Discovery with Provable Guarantees” used neural-network verification to define input-domain robustness, robust patching, and several notions of minimality, including quasi-minimality, local minimality, subset-minimality, and cardinal-minimality (Hadad et al., 18 Feb 2026). Its verification-based circuits achieved $32{,}000$6 certified robustness across MNIST, CIFAR-10, GTSRB, and TaxiNet, whereas sampling-based or heuristic patching methods had much lower robustness under the same settings. The paper also established theoretical links between monotonic faithfulness predicates and stronger minimality guarantees, and connected cardinally minimal circuits to minimum hitting set structure.

Efficiency improvements have therefore had to confront faithfulness explicitly. EAP’s speed advantage comes from approximation, but on Docstring the correlation between attribution and activation-patching scores was only $32{,}000$7, with a best-fit slope of about $32{,}000$8, and KL divergence could induce a zero-gradient failure mode (Syed et al., 2023). PAHQ took the opposite route: it preserved patching-based ACDC but reduced the cost of each patching operation through per-attention-head mixed-precision execution and a three-stream CUDA scheduler. On IOI, PAHQ reduced GPT-2 runtime from $32{,}000$9 to $9$0 and memory from $9$1 GB to $9$2 GB, with faithfulness much closer to ACDC than direct quantization; the paper summarized this as up to roughly $9$3 runtime reduction and over $9$4 memory reduction, while showing that $9$5-bit precision was disastrous and $9$6-bit was the practical regime (Wang et al., 27 Oct 2025).

4. Photonic and quantum circuit synthesis

In photonic quantum computing, automated circuit discovery has been formulated as differentiable inverse design over passive linear optics. For fusion-based photonic quantum computation with dual-rail encoding and heralded passive optics, “Automated discovery of heralded ballistic graph state generators” parameterized an $9$7 unitary as

$9$8

optimized a probability-weighted Bures-angle objective over heralded ancilla outcomes, and then sparsified the dense solution into a compact beamsplitter fabric (Hartnett et al., 22 Aug 2025). The method relied on polynomial-based strong simulation using FFT-based multivariate polynomial multiplication, followed by a second-pass regularizer that drove beamsplitter angles toward trivial or SWAP-equivalent values. It discovered optimized $9$9-, $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$0-, and $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$1-qubit graph-state circuits, achieved $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$2-qubit success probabilities from $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$3 to $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$4 and $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$5-qubit success probabilities from $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$6 to $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$7, outperformed the unboosted fusion baseline by up to $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$8 and $$\Delta_e L = \left(e_{\text{corr}} - e_{\text{clean}}\right)^\top \frac{\partial}{\partial e_{\text{clean}}} L\bigl(\mathrm{do}(E=e_{\text{clean}})\bigr).$$9, and produced the first known circuits for several $\left|\Delta_e L\right|$0-qubit states (Hartnett et al., 22 Aug 2025).

Other quantum-synthesis approaches emphasize different search biases. The multi-objective evolutionary method of 2018 searched over variable-length genomes, used Pareto ranking and elitist archiving, rediscovered textbook QFT and Grover circuits, and also found shorter approximate QFTs and a divide-and-conquer family of $\left|\Delta_e L\right|$1-qubit Grover circuits (Potoček et al., 2018). Reinforcement learning for fault-tolerant logical state preparation instead used stabilizer tableaux as observations and reward shaping for correctness, flagging, and ancilla product-state separation; it found circuits with fewer gates and flag qubits than published results, discovered integrated fault-tolerant constructions with $\left|\Delta_e L\right|$2 for distance-$\left|\Delta_e L\right|$3 codes, and handled realistic connectivity constraints up to $\left|\Delta_e L\right|$4 physical qubits (Zen et al., 2024). A further hierarchical variant mined repeated connected closed subgraphs from RL-generated encoders, identified gadget families such as the DCX, PL, and O families, and promoted them to macro-actions that improved search speed or final gate counts depending on the family (Yevtushenko et al., 29 Sep 2025).

Generative and screening-based formulations have also appeared. FlowQ-Net casts quantum circuit synthesis as reward-proportional generative modeling over circuit trajectories with a GFlowNet, using trajectory balance and a bi-level loop in which continuous gate parameters are optimized after a discrete architecture is sampled. Across VQE, Max-Cut, and image classification, it produced circuits reported as $\left|\Delta_e L\right|$5–$\left|\Delta_e L\right|$6 more compact in parameters, depth, and gate count than standard unitary baselines while maintaining accuracy and remaining competitive under IBM noise profiles (Dai et al., 30 Oct 2025). CircuitHunt, by contrast, treats discovery as budget-aware screening over a dataset of candidate circuits. It filters KetGPT circuits by qubit count, trainable-gate presence, parameter budget, and executability, embeds each candidate into a standardized hybrid QNN, and ranks candidates by validation macro-F1 after short training. On credit-card fraud detection, the selected circuit achieved $\left|\Delta_e L\right|$7 test accuracy, a high macro-F1 score, and ROC-AUC $\left|\Delta_e L\right|$8, while reducing architecture-search time from days to hours (Innan et al., 29 Aug 2025).

5. Analog and superconducting circuit discovery

Automated circuit discovery in analog and superconducting hardware is distinguished by explicit structural and fabrication constraints. SCILLA organizes superconducting-circuit design as a closed-loop workflow with three modules—design or proposal, property calculation by Hamiltonian simulation, and merit evaluation—coordinated asynchronously over a database (Menke et al., 2019). In its $\left|\Delta_e L\right|$9-local coupler application, the search reduced the target to a spectral signature: a double-well ground-state energy profile with large peak height and excited-state splitting and low noise sensitivity. After random sampling and particle-swarm refinement, SCILLA discovered circuit C, a two-loop coupler with refined metrics $x=\beta+\gamma$0, $x=\beta+\gamma$1, and $x=\beta+\gamma$2; in full simulation it yielded an effective $x=\beta+\gamma$3-body interaction strength $x=\beta+\gamma$4 and reduced asymmetry relative to peak height by a factor of $x=\beta+\gamma$5 compared to the prior proposal (Menke et al., 2019).

AnalogGenie treats analog topology generation as sequence modeling over pin-level graphs. Its core contributions are a curated dataset of $x=\beta+\gamma$6 distinct topologies from $x=\beta+\gamma$7 circuit types, a pin-level graph representation that removes ambiguous device-level connectivity, and an Eulerian-circuit sequence encoding that stores only existing edges (Gao et al., 28 Feb 2025). Augmentation based on multiple Eulerian traversals increased data volume by about $x=\beta+\gamma$8; the pretrained-and-finetuned model then reached $x=\beta+\gamma$9 valid generated circuits, more than $\beta$0 topology types, maximum size $\beta$1 devices, novelty $\beta$2, and reported figures of merit $\beta$3 for Op-Amps, $\beta$4 for power converters, and $\beta$5 for bandgaps (Gao et al., 28 Feb 2025). The paper’s framing is explicitly about topology synthesis as the most creative and least automated phase of analog design.

AnalogFed extends this program to private, decentralized datasets. It federates an AnalogGenie-style decoder-only transformer under FedAvg, introduces graph simplification, frequent-subgraph tokenization with gSpan, and traversal shortening via the Chinese Postman Problem, and reports an average compression rate of about $\beta$6 relative to the original representation (Li et al., 20 Jul 2025). With the full dataset, centralized validity was $\beta$7; under federated training it remained close, with $\beta$8 validity for $\beta$9 clients and $\gamma$0 for $\gamma$1 clients, while preserving raw-data privacy. The same work also describes a two-stage privacy strategy—federated pre-training plus decentralized PPO-based fine-tuning on process-specific data—and evaluates poisoning attacks together with an FLDetector-inspired defense (Li et al., 20 Jul 2025).

6. Recurring patterns and research directions

Across these literatures, automated circuit discovery repeatedly decomposes into four layers: representation, objective, search, and reduction. Representation determines what the search can even express: DAG edges for ACDC, token-position-specific edges and schemas for PEAP, SAE features and Transcoders for linear computation graphs, beamsplitter fabrics for photonics, pin-level graphs and Eulerian sequences for analog topologies, and repeated subgraphs as gadgets in RL (Conmy et al., 2023, Haklay et al., 7 Feb 2025, Ge et al., 2024, Hartnett et al., 22 Aug 2025, Gao et al., 28 Feb 2025, Yevtushenko et al., 29 Sep 2025). Objectives then formalize what counts as a successful circuit, ranging from KL divergence, logit-difference preservation, and causal interchangeability to heralded success probability, figure of merit, or spectral robustness. Search may be greedy pruning, gradient descent on a unitary manifold, PPO, GFlowNet sampling, evolutionary Pareto optimization, or federated aggregation. Reduction or compilation finally turns a dense or redundant solution into something interpretable or fabricable, as in beamsplitter sparsification, majority-vote cores across repeated extractions, or gadget promotion to macro-actions.

A recurring substantive result is non-uniqueness. In mechanistic interpretability, repeated extractions within the same condition can differ structurally while remaining functionally interchangeable, supporting the claim that discovery algorithms often sample from an equivalence class rather than recovering a unique mechanism (Makou et al., 4 Jun 2026). In quantum synthesis, evolutionary search and GFlowNet sampling likewise return multiple circuits with the same functionality but different trade-offs in depth, oracle calls, or robustness (Potoček et al., 2018, Dai et al., 30 Oct 2025). This suggests that structural minimality and mechanistic uniqueness should not be conflated.

Future directions identified in the literature remain heterogeneous but coherent. Vision work proposes automatic selection of circuit width and broader circuit shapes beyond strict layerwise topology (Rajaram et al., 2024). Quantum-search work calls for moving from fixed-size circuits toward scalable algorithmic families and richer hybrid optimization (Potoček et al., 2018). Verification-based interpretability remains limited by the cost of neural-network verification, even as it offers the strongest current guarantees (Hadad et al., 18 Feb 2026). Federated analog discovery raises unresolved questions about privacy proofs, secure aggregation, and robustness under more general adversaries (Li et al., 20 Jul 2025). Taken together, these programs indicate that automated circuit discovery is converging on a general inverse-design perspective: circuits are discovered not by local intuition alone, but by optimizing explicit behavioral predicates over structured search spaces, with increasing emphasis on faithfulness, sparsity, hardware realism, and formal guarantees.