OpenACMv2: Accuracy-Constrained DCiM Framework

• OpenACMv2 is an open, accuracy-constrained co-optimization framework for approximate digital compute-in-memory, integrating explicit application-level error budgets.
• It employs a two-level ACCO decomposition that combines architecture-level search using a PEA-GNN surrogate with variation-aware transistor sizing for rapid, robust design space exploration.
• The framework leverages open-source tools like OpenROAD and FreePDK45 to achieve reproducible design and optimization of SRAM-based processing elements under strict PPA and accuracy constraints.

Searching arXiv for the cited OpenACMv2 and predecessor papers to ground the article. OpenACMv2 is an open, accuracy-constrained co-optimization framework for approximate Digital Compute-in-Memory (DCiM) that treats application-level accuracy budgets as explicit design constraints while optimizing power–performance–area (PPA) across architecture and transistor-level decisions. It builds on OpenACM’s SRAM-based approximate CiM compiler and OpenYield’s variation-aware SRAM analysis, and is compatible with FreePDK45 and OpenROAD for reproducible evaluation and rapid “what-if” exploration under controlled error budgets (Zhou et al., 13 Mar 2026). In this setting, DCiM denotes digital arithmetic performed in or near SRAM-based processing elements (PEs) to reduce data movement, while approximation refers to deliberate use of error-tolerant arithmetic structures such as approximate compressors and multipliers to improve energy efficiency (Zhou et al., 16 Jan 2026).

1. Conceptual basis and design objectives

OpenACMv2 is motivated by the observation that approximate DCiM does not admit a clean separation between arithmetic approximation, memory organization, and circuit implementation. Approximate compressors and multipliers embedded in DCiM PEs can reduce power and area, but the resulting PPA–accuracy trade-offs depend simultaneously on multiplier topology, partial-product truncation, SRAM organization, and device sizing, and they are sensitive to process, voltage, and temperature variation. The framework therefore formulates an explicitly constrained design problem in which accuracy is not a post hoc validation metric but a first-class constraint during optimization (Zhou et al., 13 Mar 2026).

The underlying optimization target is called Accuracy-Constrained Co-Optimization (ACCO). Let the design vector $x$ consist of architecture variables and circuit variables. Architecture variables include approximate multiplier choices, represented by a compressor assignment vector $a$, and SRAM macro organization, represented as $s = (r, c, \mu, n_a)$. Circuit variables include transistor widths for standard-cell compressors $w$ and SRAM bitcell sizing parameters $u$. OpenACMv2 then defines PPA objectives through dynamic power $P(x)$, worst-case delay $D(x)$, area $A(x)$, and power-delay product $PDP(x) = P(x)\cdot D(x)$, while expressing arithmetic fidelity through Mean Relative Error Distance (MRED) and Normalized Mean Error Distance (NMED) (Zhou et al., 13 Mar 2026).

The framework supports both single-objective and multi-objective constrained formulations. The single-objective form is

$$\min_x PDP(x)\quad \text{subject to}\quad Acc(x)\ge \alpha \ \text{or}\ Err(x)\le \epsilon,$$

while the multi-objective form is

$a$0

A penalty form is also defined:

$a$1

This formulation makes explicit that OpenACMv2 is not merely a compiler extension but a constrained design-space exploration system for approximate DCiM (Zhou et al., 13 Mar 2026).

2. Two-level ACCO decomposition

The framework decomposes ACCO into two coupled but tractable levels. Level-1 performs architecture search under accuracy constraints; Level-2 performs variation- and PVT-aware transistor sizing for the selected logic and memory structures. This decomposition is central to the method because the joint architecture–transistor space is described as large and nonconvex, while brute-force evaluation with synthesis, timing, and power analysis for every candidate is too slow (Zhou et al., 13 Mar 2026).

At Level-1, the search space includes approximate multiplier compressor combinations and SRAM macro parameters. For an $a$2-bit multiplier, partial-product columns are indexed by $a$3. Approximation is restricted to lower-significance columns $a$4, while higher-significance columns $a$5 remain exact. A set of configurable compressor slots is assigned compressor types from a library, producing an architecture encoding $a$6 with discrete search-space size $a$7. The final stage is a carry-propagate adder (CPA). In parallel, SRAM macro parameters are explored through $a$8 under a capacity constraint $a$9 (Zhou et al., 13 Mar 2026).

The top-level architecture objectives are defined separately for arithmetic and SRAM. For approximate multipliers, the paper states

$s = (r, c, \mu, n_a)$0

For SRAM, the objective is

$s = (r, c, \mu, n_a)$1

with $s = (r, c, \mu, n_a)$2 and $s = (r, c, \mu, n_a)$3. Constraint handling is integrated into NSGA-II, MOEA/D, SMAC, and MOBO, so that feasible designs dominate infeasible ones or are explicitly penalized when they violate the error budget (Zhou et al., 13 Mar 2026).

Level-2 then refines the shortlisted Level-1 architectures through transistor sizing. For compressors, the design vector groups transistor widths into symmetry or width-sharing sets for gates such as INV, NAND/NOR, XOR/XNOR, and AOI/OAI. SPICE simulation is used to verify functional correctness against the truth table of each compressor. The stated objective is to minimize $s = (r, c, \mu, n_a)$4 subject to correctness for all inputs, width bounds, and optionally worst-case PVT robustness. For SRAM, the framework follows OpenYield’s SPICE-based, PVT-aware Monte Carlo approach to optimize robustness-centric figures of merit while aggregating worst-case SNM, read/write delay, and power (Zhou et al., 13 Mar 2026).

A notable implication of this decomposition is that Level-1 determines the arithmetic error profile, whereas Level-2 must preserve function. The paper states that Level-2 sizing must preserve function so arithmetic error remains unchanged, keeping task accuracy intact. This separates accuracy budgeting from device-level robustness optimization in a controlled way (Zhou et al., 13 Mar 2026).

3. Accuracy metrics, error modeling, and search constraints

OpenACMv2 formalizes arithmetic error through MRED and NMED. The definitions are

$s = (r, c, \mu, n_a)$5

over $s = (r, c, \mu, n_a)$6, and

$s = (r, c, \mu, n_a)$7

with $s = (r, c, \mu, n_a)$8 (Zhou et al., 13 Mar 2026).

These metrics are used as optimization constraints rather than as descriptive summaries alone. The design budget may be given as an upper bound on NMED or MRED, or as a task-level accuracy requirement such as Top-1 or Top-5 accuracy. At Level-1, feasible candidates are ranked by PDP or by a multi-objective PPA criterion only if their predicted error falls within the specified budget. The framework therefore converts application tolerance into admissible approximate arithmetic design regions (Zhou et al., 13 Mar 2026).

The paper also distinguishes arithmetic error from task-level accuracy. For neural-network inference, architectural error is mapped empirically to model accuracy, with the framework enforcing $s = (r, c, \mu, n_a)$9 during search and then validating the selected designs on downstream tasks such as CIFAR-10. This separation is methodologically important: it prevents PPA optimization from exploiting approximate circuits whose low-level error statistics may be acceptable in aggregate but violate the imposed budget (Zhou et al., 13 Mar 2026).

A frequent misconception is that approximate DCiM can be optimized by minimizing arithmetic error alone. OpenACMv2’s formulation rejects that view. The constrained objective shows that low error by itself is not the target; rather, the target is minimum PPA within a feasible error region. The paper explicitly notes that accuracy constraints cut off the low-error tail, avoiding over-precision and shifting search toward energy-optimal approximate designs within feasible error regions (Zhou et al., 13 Mar 2026).

4. PEA-GNN surrogate for architecture-level exploration

Level-1 architecture exploration is accelerated by a graph neural network surrogate called PEA-GNN. The need for such a surrogate follows directly from the cost of conventional synthesis and sign-off evaluation across a combinatorial candidate space. OpenACMv2 uses PEA-GNN to predict arithmetic error and PPA jointly, providing a learned proxy for near-EDA evaluation during search (Zhou et al., 13 Mar 2026).

The surrogate input is a graph representation $w$0 of the multiplier reduction tree, aligned with stages $w$1. Nodes correspond to combinational blocks, including half adders, full adders, and exact or approximate 4:2/3:2 compressors. Edges represent signals, and stage structure follows the hierarchy of the compression cascade. Node features are constructed from block truth tables and input-bit marginal probabilities. For a node variant $w$2, the truth table is denoted $w$3, the weighted input distribution is encoded through $w$4, and the fused node feature is

$w$5

where $w$6 and $w$7 captures bit-level deviation from the exact block (Zhou et al., 13 Mar 2026).

Message passing follows a stage-wise GraphSAGE formulation:

$w$8

with learnable matrices $w$9, nonlinearity $u$0, and mean aggregation. After $u$1 stages, embeddings of “critical” nodes, defined as approximate nodes and last-stage nodes, are concatenated into a global representation $u$2, which is then passed to a shared MLP regression head. The predicted outputs are

$u$3

and Softplus is used to ensure non-negativity (Zhou et al., 13 Mar 2026).

Training data are automatically generated multiplier designs synthesized with OpenROAD/OpenSTA under a 5 ns clock and 10 fF load. The model is implemented with PyTorch and PyTorch Geometric, trained using Adam, and optimized with a multi-task MSE loss

$u$4

The reported fidelity is high. For 8-bit designs, MRED/NMED mean relative errors are 2.17%/1.84%, Delay/Area/Power errors are $u$5, $u$6, and runtime is 0.26 s versus 37 s, corresponding to a 142× speedup. For 16-bit designs, MRED/NMED errors are 4.73%/2.30%, PPA deviations are $u$7, $u$8, and runtime is 0.25 s versus 116 s, corresponding to a 464× speedup (Zhou et al., 13 Mar 2026).

This suggests that the surrogate is not simply a convenience layer but an enabling component for constrained Pareto exploration. Without it, the framework’s stated goal of rapid “what-if” exploration would be difficult to realize at practical search budgets.

5. Circuit-level sizing, robustness, and reproducible tool flow

The second level of OpenACMv2 focuses on variation- and PVT-aware transistor sizing for both approximate logic and SRAM. For compressor standard cells, transistor widths are grouped according to symmetry and width-sharing constraints, and SPICE simulations are used to verify that output voltages, interpreted through technology thresholds $u$9, reproduce the intended truth table for every input pattern. The optimization target is stated as minimizing $P(x)$0 while maintaining correctness and respecting width bounds; worst-case metrics over PVT corners can also be included (Zhou et al., 13 Mar 2026).

For SRAM, OpenACMv2 uses OpenYield’s SPICE-based Monte Carlo methodology. Device-level variations are modeled according to the supported PDK and model assumptions, and yield is estimated statistically as

$P(x)$1

The framework aggregates mean and variance of delay and power, worst-case performance across PVT, and confidence intervals where enabled. The stated purpose is to improve robustness by expanding margins such as SNM and minimizing worst-case delay and power without violating logic correctness (Zhou et al., 13 Mar 2026).

The digital implementation flow is fully open. OpenACMv2 is compatible with FreePDK45 and uses the Nangate45 nm open-cell library in the reported experiments. OpenROAD and OpenSTA provide synthesis, place-and-route, timing, and power analysis, while SPICE simulators such as Xyce are used for transistor-level and Monte Carlo evaluation through OpenYield. The workflow consists of specifying bit-width, compressor library, accuracy budget, and PPA objectives; running Level-1 architecture search with PEA-GNN-guided optimizers; applying Level-2 sizing to selected compressors and SRAM bitcells; integrating the final PE design; and validating PPA and task-level accuracy (Zhou et al., 13 Mar 2026).

OpenACMv2 inherits its infrastructural basis from OpenACM. The predecessor framework already provided end-to-end macro generation for SRAM-based approximate DCiM, accuracy-configurable multiplier support, variation-aware SRAM characterization, and a fully open physical design flow based on OpenROAD and FreePDK45. OpenACMv2 extends that baseline by adding unified, explicit accuracy-constrained co-optimization across architecture and transistor sizing (Zhou et al., 16 Jan 2026).

6. Experimental results, prior-art context, and limitations

The reported experiments cover surrogate fidelity, architecture-level Pareto exploration, Level-2 transistor sizing, and SRAM bank/bitcell optimization. Hardware and software used for the experiments include an Intel Xeon Gold 6330 CPU, an NVIDIA A100 GPU, PyTorch/PyG for PEA-GNN, OpenROAD/OpenSTA for digital metrics, and SPICE via OpenYield for SRAM and device-level simulations. Workloads include image blending, measured by PSNR, and CIFAR-10 image classification, measured by Top-1/Top-5 accuracy at 16-bit (Zhou et al., 13 Mar 2026).

At architecture level, the framework reports concave MRED–PDP frontiers recovered by NSGA-II, MOEA/D, SMAC, and MOBO, with MOEA/D converging most stably. In the 8-bit case, compared with the Base exact design at PDP 484 fJ and MRED $P(x)$2, ACCO selects designs that satisfy the accuracy budget and reduce PDP by approximately 2.2–2.5×, with a cited example of Case2 at 196 fJ. The associated PSNR improves as the budget tightens, with Case5 changing from 58.57 to 64.31 on Test0/Test1. In the 16-bit case, Pareto points reduce PDP from 3874 fJ for the Base design to approximately 1.2–1.3 pJ for Case1–Case5 at Level-1, described as an approximately 3× improvement, while CIFAR-10 Top-1/Top-5 remains within $P(x)$3 of Base, with Case4 reported at 66.5%/86.7% versus Base 66.6%/86.7% (Zhou et al., 13 Mar 2026).

At Level-2, transistor sizing provides additional but smaller gains. For compressors, MOEA/D is reported to push PDP–Area fronts left of the baseline for all eight compressor types, and on Sabetz it dominates other algorithms. Across example cases, PDP is reduced modestly, such as 193 to 191 fJ and 214 to 206 fJ in 8-bit designs, while preserving correctness and leaving MRED unchanged. For SRAM, architecture-level exploration yields concave power–delay Pareto fronts, whereas Level-2 bitcell sizing provides limited delay and power reductions compared with architecture gains; the paper states that architecture choices dominate SRAM PPA, while device-level tuning gives incremental improvements and area reductions (Zhou et al., 13 Mar 2026).

In relation to prior work, OpenACMv2 is positioned against AutoDCIM, SynDCIM, ARCTIC, and OpenC², which are described as targeting exact arithmetic and lacking explicit accuracy-aware rapid evaluation for approximate arithmetic. Relative to OpenACM, the new framework adds ACCO decomposition, PEA-GNN surrogate modeling, and variation-aware logic and SRAM sizing under explicit accuracy budgets (Zhou et al., 13 Mar 2026). OpenACM itself had already shown that integrating approximate multipliers into an open DCiM flow could achieve up to approximately 64% power reduction at 32-bit with negligible accuracy loss on ResNet-18, but its policy remained user-driven and lacked a built-in automated design-space exploration engine (Zhou et al., 16 Jan 2026).

The limitations are also stated explicitly. PEA-GNN is trained at nominal corners; throughput, leakage, IR drop, routing congestion, and post-layout parasitics are not fully integrated into the objective set; place-and-route, parasitic extraction, and crosstalk are only partially covered in backend sign-off; SRAM macro/periphery co-optimization remains limited; and the demonstrations are confined to 8/16-bit multipliers and 45 nm flows. A plausible implication is that extending the framework to advanced nodes, broader PVT-aware surrogate models, and larger bit-widths will require retraining and further flow calibration rather than simple parameter transfer (Zhou et al., 13 Mar 2026).