AnalogTester: Efficient Test Abstraction

Updated 6 July 2026

AnalogTester is a research theme that abstracts complex analog testing into computational and hardware frameworks, reducing cost and setup time.
It encompasses methods like epsilon-SVM-based specification compaction, DNN-driven indirect testing, and LLM-based automatic testbench generation for analog circuits.
The framework spans production testing, design automation, and laboratory instrumentation by leveraging statistical inference, deep learning, and embedded hardware.

AnalogTester designates a set of analog-testing methodologies and platforms whose common concern is the conversion of expensive, topology-specific, or difficult-to-access analog validation tasks into more tractable computational or hardware procedures. In the cited literature, the name is used both for an $\epsilon$ –SVM-based framework for specification test compaction in analog circuits and MEMS and for a LLM-based framework for automatic testbench generation in analog circuit design; related work extends the same problem space through deep-learning-based indirect testing, wrapped analog-core access in mixed-signal SoCs, offline analog signal emulation, RF boundary modules, DAC experimentation platforms, and programmable-gain waveform digitization instruments (0710.4719, Chen et al., 14 Jul 2025).

1. Scope and research usage

The literature associates AnalogTester with several distinct technical roles rather than a single invariant implementation. Some variants operate at production-test level, some at design-automation level, and some as laboratory or commissioning hardware. What unifies them is the attempt to reduce analog test cost, shorten setup time, or make measurements available through more convenient abstractions.

Usage	Core mechanism	Source
Specification test compaction	$\epsilon$ –SVM pass/fail classification with guard-banding	(0710.4719)
Offline commissioning hardware	ZYNQ SoC, DAC8532, DG636, 128 strip outputs, dose and environmental signals	(Huang et al., 2023)
Indirect performance testing	Per-module DNNs, 0–1 integer programming, aggregation DNN	(Cao et al., 2024)
Mixed-signal SoC access	Analog wrappers, unified digital TAM, rectangle-packing scheduling	(0710.4686)
Automatic testbench generation	Multimodal extraction, template RAG, TED code generation, Verilog-A validation	(Chen et al., 14 Jul 2025)

This range suggests that AnalogTester is best understood as a research theme centered on analog test abstraction: redundant specifications may be inferred statistically, inaccessible internal analog behavior may be wrapped or emulated, and paper-level design descriptions may be translated into executable verification artifacts.

2. Specification compaction and pass/fail inference

In analog and MEMS production test, specification-based testing remains the de facto standard because there are no universally accepted fault models for analog/MEMS. The cost burden arises because each specification may require elaborate stimuli, precision instrumentation, temperature control, and long settling times. The 2007 AnalogTester framework starts from the complete specification-based test set $T=\{t_1,\dots,t_n\}$ with specification values $S=\{s_1,\dots,s_n\}$ and acceptable ranges $R_i=[L_i,U_i]$ , labels a device as $y\in\{+1,-1\}$ depending on whether all measured $s_i$ fall in range, and then eliminates redundant tests by framing compaction as a pass/fail classification problem rather than multi-target regression (0710.4719).

The method normalizes each specification by

$s_i'=\frac{s_i-L_i}{U_i-L_i},$

treats the remaining specification measurements as features, and trains a soft-margin SVM with kernels to predict the pass/fail effect of the eliminated specifications. The primal optimization is

$\min_{w,b,\xi}\ \frac{1}{2}\|w\|^2 + C\sum_{i=1}^{N}\xi_i$

subject to

$y_i(w^T\phi(x_i)+b)\ge 1-\xi_i,\qquad \xi_i\ge 0.$

Training is accelerated by grid-based compaction of the normalized feature space: cells containing both good and bad labels are retained, while pure cells are merged to representative center points. Test elimination is greedy, validation proceeds by cross-validation or held-out validation across lots and temperatures, and a guard-band region $\epsilon$ 0 is created from perturbed decision models so that devices falling near the decision boundary are routed to additional testing rather than being decided solely by the compacted classifier.

Risk is quantified through defect escape and yield loss. For a compacted set $\epsilon$ 1,

$\epsilon$ 2

which are computed from the confusion matrix as

$\epsilon$ 3

Reported case studies established the practical range of the approach. For an operational amplifier, 5 of 11 specification-based tests were eliminated with defect escape $\epsilon$ 4 and yield loss $\epsilon$ 5. For a MEMS accelerometer, elimination of hot and cold tests using room-temperature measurements produced defect escape $\epsilon$ 6 and yield loss $\epsilon$ 7, with test cost reduced by more than half. The op-amp result depended on correlations among DC gain, 3-dB bandwidth, unity-gain frequency, slew rate, rise time, overshoot, settling time, quiescent current, CMRR-related and PSRR-related quantities, and short-circuit current; the accelerometer result depended on stable temperature dependencies in sensitivity, bias, resonance, and scale-factor drift.

3. Learned indirect testing beyond binary classification

A different line of work treats analog testing not as redundancy detection among already measured specifications but as indirect performance estimation from selected test modules. In that framework, a test module is a combination of one test circuit and one stimulus, with response

$\epsilon$ 8

and the objective is to minimize the number or cost of selected modules while guaranteeing per-specification mean-squared-error thresholds. Per-module DNNs map normalized response waveforms to a full specification vector, the selection of modules is formulated as a 0–1 integer programming problem, and a second DNN aggregates predictions from the selected modules (Cao et al., 2024).

The module-selection problem is

$\epsilon$ 9

subject to

$T=\{t_1,\dots,t_n\}$ 0

where $T=\{t_1,\dots,t_n\}$ 1 is the per-specification MSE of module $T=\{t_1,\dots,t_n\}$ 2. In the reported OPAMP study, $T=\{t_1,\dots,t_n\}$ 3 specifications were estimated: AOL-3dB, AOL, IB, CMRR, PM, GBW, PSRR, SR-R, SR-D, and VOS. The setup used 4 stimuli, 2 negative-feedback test circuits, and therefore 8 available modules. The per-module networks were 7-layer fully connected ReLU MLPs; the aggregation network was a 5-layer fully connected ReLU MLP; Adam with learning rate $T=\{t_1,\dots,t_n\}$ 4 and MSE loss was used throughout.

The optimization selected 3 modules, namely $T=\{t_1,\dots,t_n\}$ 5, $T=\{t_1,\dots,t_n\}$ 6, and $T=\{t_1,\dots,t_n\}$ 7, reducing uniform module cost from 8 to 3. The proposed selection-plus-DNN-aggregation method met the per-specification thresholds, whereas averaging predictions from all 8 modules exceeded thresholds, and weighted-sum baselines were inferior. This suggests a complementary relation to the 2007 compaction framework: one approach learns pass/fail boundaries from a complete specification set, while the other learns the specification vector itself from a sparse set of test excitations.

4. Embedded hardware, boundary access, and laboratory instrumentation

AnalogTester also appears in hardware forms that emulate, expose, or digitize analog behavior directly. One example is an offline ionization-chamber signal generator for proton-therapy nozzle commissioning. That system uses a Xilinx ZYNQ SoC XC7Z035, four 32-channel daughter cards for 128 strip outputs, DAC8532 for analog level generation, DG636 dual SPDT analog switches, ADAS8691 for readback, a dose output, environmental outputs, and a high-voltage sampling readback. The beam profile follows a Gaussian cross-section, 13 strips around the peak are modeled, the per-channel injected charge is

$T=\{t_1,\dots,t_n\}$ 8

and the position conversion is

$T=\{t_1,\dots,t_n\}$ 9

With PWM period $S=\{s_1,\dots,s_n\}$ 0 and front-end integration time $S=\{s_1,\dots,s_n\}$ 1, the system achieved Gaussian fits with $S=\{s_1,\dots,s_n\}$ 2-square $S=\{s_1,\dots,s_n\}$ 3, position accuracy within $S=\{s_1,\dots,s_n\}$ 4, and dose accuracy within $S=\{s_1,\dots,s_n\}$ 5 (Huang et al., 2023).

For embedded mixed-signal SoC test, wrapped analog cores are converted into “virtual digital core” abstractions by surrounding them with an ADC/DAC pair, semi-serial I/O registers, encoder/decoder logic, and a digital test controller connected to the digital Test Access Mechanism. Wrapper sharing and TAM scheduling are co-optimized through rectangle packing and a cost function

$S=\{s_1,\dots,s_n\}$ 6

with normalized area overhead

$S=\{s_1,\dots,s_n\}$ 7

A standalone 8-bit wrapper test chip in 0.5 $S=\{s_1,\dots,s_n\}$ 8m technology occupied $S=\{s_1,\dots,s_n\}$ 9, and transistor-level evaluation of a baseband filter cut-off-frequency test showed about $R_i=[L_i,U_i]$ 0 error in reconstructed spectrum relative to direct analog measurement (0710.4686).

At RF boundary-scan level, IEEE 1149.4 compatible analog boundary modules were extended with local RF-to-DC detectors so that only DC quantities travel over AB1/AB2. The reported ABMs measured power and frequency from 1 GHz to 2 GHz, with roughly 2 dB absolute power error and 0.1 GHz frequency error across temperature, supply voltage, and process variations; after process calibration, these improved to about 1 dB and about 0.05 GHz (0710.4721). The key architectural constraint is that the analog test bus is not an RF conduit; RF information must be converted locally before routing.

Laboratory and detector-calibration platforms widen the hardware interpretation further. A programmable-gain waveform digitization instrument combined a DC-coupled pre-amplifier with programmable attenuation and gain and a 12-bit ADC running up to 3.6 GSPS in time-interleaved mode, delivering DC-to-450 MHz bandwidth, ENOB above 7 bits in high gain set, and 5.8 bits in low gain set across that bandwidth (Cao et al., 2018). A separate flexible laboratory setup for DAC experimentation used a Digilent Basys-3 board with AMD Artix-7 XC7A35T-1CPG236C FPGA to compare analog multiplexing, high-speed single-DAC operation, $R_i=[L_i,U_i]$ 1 modulation with time interleaving, and Dynamic Element Matching under common instrumentation and load conditions (Vega-Leal et al., 2 Feb 2026).

5. Automatic testbench generation from papers

The 2025 AnalogTester framework shifts the locus of analog testing from production and instrumentation to EDA automation. It is a LLM-based, multi-agent framework that automatically builds analog testbenches directly from academic papers and generates executable testbenches in the Tsinghua Electronic Design environment. Its pipeline contains four stages: domain-knowledge integration, paper information extraction, simulation scheme synthesis, and TED testbench code generation with validation against “golden” Verilog-A models (Chen et al., 14 Jul 2025).

Domain-knowledge integration produces a template repository of 36 templates across op-amps, bandgap references, and LDOs, together with a TED knowledge base of 72 functions. Paper information extraction uses a multimodal LLM agent to parse text, figures, and tables and to produce a JSON list of experiments and specifications with fields for circuit name, analysis type, stimuli, loads, measurement targets, figure or table citations, and PVT conditions. Simulation scheme synthesis retrieves and refines templates by Retrieval-Augmented Generation, and TED code generation uses RAG against the function database, chain-of-thought decomposition by metric, replacement of the DUT with golden Verilog-A, automatic syntax and functional checks, and iterative error repair. New templates and new Verilog-A models are not inserted automatically; human validation is required before repository inclusion.

The reported benchmark covered 8 papers and 63 experiments: 23 for op-amps, 18 for BGRs, and 22 for LDOs. Information Extraction achieved 84% success with average 123 s per experiment, Experiment Scheme Generation 86% with average 165 s, and Testbench Code Generation 89% with average 126 s. An OTA case in TSMC 65 nm showed near-perfect agreement between TED-generated and Cadence testbenches on 11 metrics, including Gain 71.1 dB, UGW 33.1 kHz, PM 75.3°, linear swing 0.03–0.58 V, SR 30.9 V/ms, CMRR@100 Hz 85.7 dB, PSRR@100 Hz 63.0 dB, Power 365 nW, THD@520 mVpp 0.31%, and minimum supply 0.6 V. Ablations showed that iteration together with the TED function database yielded 100% syntax pass and more than 80% functional success, whereas single-pass generation achieved less than 22% functional success and removing the TED function database caused functional verification to fail completely.

6. Metrics, safeguards, limitations, and future directions

Across its variants, AnalogTester is defined as much by governance mechanisms as by core algorithms. In specification compaction, the principal safeguards are defect escape, yield loss, guard-band size, conservative $R_i=[L_i,U_i]$ 2, decision thresholds on $R_i=[L_i,U_i]$ 3 and $R_i=[L_i,U_i]$ 4, production revalidation across lots and temperatures, and rollback when drift exceeds thresholds (0710.4719). In testbench-generation form, correctness depends on syntax checks, functional checks against golden Verilog-A, iterative auto-repair, and human-in-the-loop validation for new templates and new VA models (Chen et al., 14 Jul 2025). In RF boundary-scan form, the governing limitation is architectural: IEEE 1149.4 cannot transport RF directly and must operate through RF-to-DC extraction (0710.4721). In learned indirect testing, module abundance is not automatically beneficial, since the benchmark using average predictions from all 8 modules failed the accuracy requirements (Cao et al., 2024).

Cost modeling is likewise heterogeneous. The original compaction framework models cost savings by comparing

$R_i=[L_i,U_i]$ 5

with

$R_i=[L_i,U_i]$ 6

and gives an accelerometer example in which tri-temperature testing cost for 1,000 units drops from \$R_i=[L_i,U_i]$71168, or about 54% savings (0710.4719). The mixed-signal SoC wrapper methodology collapses area and schedule length into $R_i=[L_i,U_i]$8, allowing area-dominant or time-dominant planning regimes (0710.4686). Hardware-in-the-loop platforms report fidelity through Gaussian $R_i=[L_i,U_i]$9-square, position error, dose error, bandwidth, ENOB, THD, SFDR, SINAD, or equivalent analog metrics depending on application (Huang et al., 2023, Cao et al., 2018).

The forward trajectory in the literature remains plural. Statistical compaction emphasizes periodic retraining, continuous SPC monitoring, and phased elimination on new silicon revisions. Wrapped-core methodologies call for placement-aware routing-overhead estimation and incorporation of converter self-test cost. Hardware platforms propose higher-resolution DACs, lower-leakage analog switches, adaptive Gaussian generation, dual-axis output, and closed-loop calibration with the front-end. The LLM-based framework proposes extension to PLLs, ADCs, VCOs, and comparators, improved figure parsing, broader EDA integration, and fine-tuning on the generated corpora (0710.4719, 0710.4686, Huang et al., 2023, Chen et al., 14 Jul 2025). Taken together, these directions indicate that AnalogTester is not a single mature artifact but an evolving class of methods for reducing the analog-testing bottleneck through statistical inference, embedded access, hardware emulation, and automated verification synthesis.