Large Circuit Models in AI-native EDA
- Large Circuit Models (LCMs) are AI-native foundation models that integrate diverse circuit representations—functional, structural, and layout—for advanced hardware design.
- They employ both encoder-based and decoder-based architectures, using graph transformers and LLMs to align specifications, netlists, and layouts while optimizing PPA outcomes.
- LCMs drive novel applications in early design quality, automated verification, and circuit synthesis, while addressing challenges like data scarcity and representation reliability.
Large Circuit Models (LCMs) are AI-native foundation models for electronic design automation that are intended to operate over multi-modal circuit data rather than primarily over text. In the most ambitious formulation, they are meant to natively encode and reason over heterogeneous circuit representations spanning functional specifications, RTL, gate-level netlists, and layouts, while preserving electrical, timing, and geometric fidelity (Chen et al., 2024). In the survey literature, the closely related term “circuit foundation models” (CFMs) is used as a broader umbrella covering both encoder-based pre-trained circuit models and decoder-based LLM-style generative systems; within that framing, LCM was introduced earlier as an envisioned framework of multiple aligned encoder-based circuit foundation models, each devoted to one design stage (Fang et al., 28 Mar 2025). The resulting research area sits between representation learning, multimodal reasoning, formal hardware semantics, and workflow automation, and is increasingly discussed as a possible route from AI4EDA toward AI-native EDA (Xu et al., 5 Sep 2025).
1. Conceptual emergence and scope
The defining claim behind LCMs is that hardware is not just language. A circuit simultaneously has functionality or logic, topology or structure, geometry or physical layout, timing, power, and other physical and manufacturing constraints; consequently, a circuit model that only linearizes artifacts as text is structurally incomplete for core EDA tasks (Xu et al., 5 Sep 2025). This motivates the shift from AI4EDA, where machine learning augments isolated steps such as timing estimation or script generation, toward AI-native EDA, where representation learning is embedded in the design process itself and aligned across abstraction levels (Chen et al., 2024).
Within the survey taxonomy, CFMs are defined by a two-stage paradigm: self-supervised pre-training on large amounts of unlabeled circuit data to learn intrinsic circuit properties, followed by efficient fine-tuning or adaptation for downstream applications such as early-stage design quality evaluation, circuit-related context generation, and functional verification (Fang et al., 28 Mar 2025). That definition is broader than the original encoder-centric LCM perspective, but the overlap is substantial: in practice, current discussions of LCMs usually include both encoder-based circuit representation models and decoder-based large generative models that operate on circuit artifacts.
The phrase also has an older, non-foundational meaning in classical circuit simulation. In model order reduction, “large circuit models” can refer to very large descriptor systems arising from modified nodal analysis of RLC networks, including industrial IBM power grids with up to states and $1000$ ports (Chatzigeorgiou et al., 2020). In contemporary EDA-AI usage, however, LCM denotes foundation-scale models for understanding, generating, aligning, or optimizing circuit representations rather than reduced-order dynamical macromodels.
2. Data modalities, representations, and architectural principles
LCMs are motivated by several properties of circuit data that distinguish it from ordinary NLP or vision corpora. The survey literature emphasizes equivalence across design stages, multimodality, multiple objectives such as power, performance, and area, inherently parallel execution semantics, hierarchical and heterogeneous structure, physical constraints, and severe data scarcity under proprietary IP regimes (Fang et al., 28 Mar 2025). These properties explain why generic language or vision backbones are rarely sufficient without circuit-specific adaptation.
The dominant architectural split is between encoder-based and decoder-based models. Encoder-based CFMs perform circuit representation learning for predictive tasks, typically using GNNs, graph transformers, or graph-language hybrids over CDFGs, AST-derived graphs, AIGs, post-synthesis netlists, heterogeneous layout graphs, and related structured artifacts (Fang et al., 28 Mar 2025). Decoder-based systems adapt LLMs or code models for generative tasks such as RTL generation, assertion generation, design-flow scripting, debugging, or analog topology synthesis. The survey’s central claim is that both classes belong to the same foundation-model ecosystem, but they emphasize different outputs: embeddings and predictors on the encoder side, generative interfaces and workflow automation on the decoder side (Fang et al., 28 Mar 2025).
The AI-native EDA position paper makes the alignment problem explicit by proposing three main phases of multimodal circuit representation alignment: Spec-HLS-RTL Representation Alignment, RTL-Netlist Representation Alignment, and Netlist-Layout Representation Alignment (Chen et al., 2024). In that formulation, each design stage is treated as a distinct modality with its own unimodal pre-training, followed by fusion through shared representation spaces, cross-modal pre-training, contrastive learning, mask-and-prediction training strategies, and attention-based alignment. The same paper argues that such alignment is necessary because circuit transformations must preserve design intent while admitting multiple implementation choices with different PPA outcomes (Chen et al., 2024).
The panel literature sharpens the distinction between LLMs and LCMs. LLMs are presented as strongest when the task still looks like language or code—interpreting intent, generating HDL, generating assertions and testbenches, summarizing reports, retrieving documentation, or scripting—whereas LCMs are proposed for tasks where textual linearization is inadequate, including circuit structure, hierarchical context, physical consequences, and nonlocal PPA interactions (Xu et al., 5 Sep 2025). A concise formulation from that discussion is Qiang Xu’s “What vs. How” split: LLMs for the “What,” namely capturing human intent from natural language, and LCMs for the “How,” namely mapping that intent into optimized and correct implementations (Xu et al., 5 Sep 2025).
3. Representative model families and systems
Most concrete systems now associated with LCMs remain task-specific, domain-adapted pipelines rather than universal circuit-native foundation models. They nevertheless instantiate important design patterns: graph-aware serialization, circuit-specific reward signals, retrieval grounding, multi-agent decomposition, and structured outputs.
| Work | Role | Scope |
|---|---|---|
| “CIRCUITSYNTH” (Vijayaraghavan et al., 2024) | Topology generation | Power converters |
| “AUTOCIRCUIT-RL” (Vijayaraghavan et al., 3 Jun 2025) | RL-refined topology synthesis | Switching power converters |
| “CircuitLM” (Hasan et al., 8 Jan 2026) | Multi-agent prompt-to-schematic pipeline | Microcontroller-centric designs |
| “LLMs for Analog Circuit Design Continuum (ACDC)” (Esfandiari et al., 9 Dec 2025) | Analog layout study | Floorplanning-like transistor placement |
“CIRCUITSYNTH” formulates circuit topology generation as conditional sequence generation over incident-encoded netlists and refines a pretrained LLM with a frozen circuit-validity classifier. On 1000 unique generated topologies, its validity-aware refinement improves simulator-assessed validity and reduces duplicate generation rate from about $1.85$–$1.89$ to $1.31$, but the domain is restricted to five-device power-converter topologies with fixed operating conditions (Vijayaraghavan et al., 2024). “AUTOCIRCUIT-RL” advances the same general direction by combining instruction tuning with PPO-based RLAIF, using learned reward models for validity, efficiency, and output voltage. For 4C/5C switching power converters, the strongest configuration reaches simulator-validated validity $74.48$ and $73.96$, efficiency $71.65$ and $72.22$, overall success , and over $1000$0 success in many 6C–10C settings with only about 1,000 training examples (Vijayaraghavan et al., 3 Jun 2025).
“CircuitLM” is explicitly not presented as a standalone LCM in the strict sense, but as an LLM-centered orchestration framework. Its five stages are component identification, canonical pinout retrieval, reasoning by an electronics expert agent, CircuitJSON synthesis, and SVG visualization; grounding is supplied by a curated component database initially comprising 50 components, and validation is performed by Dual-Metric Circuit Validation with separate Library Compliance and Electrical Logicality terms (Hasan et al., 8 Jan 2026). The system achieves high library compliance across six frontier models, but the paper’s own framing is cautious: it is strongest in microcontroller-centric designs, does not run SPICE or ERC, and remains much closer to a workflow wrapper around general LLMs than to a genuine circuit-native foundation model (Hasan et al., 8 Jan 2026).
“LLMs for Analog Circuit Design Continuum (ACDC)” studies analog layout subtasks such as subgroup inference, masked placement, sequential next-transistor placement, and all-at-once placement. It reports that T5-small reaches $1000$1, $1000$2, $1000$3, and $1000$4 accuracy as the number of masked groups rises from 1 to 4, that a T5 masked-layout model attains about $1000$5 non-overlapping accuracy on synthetic data, and that GPT-oss-20B with a more realistic continuous-coordinate representation transfers better to real netlists than smaller models (Esfandiari et al., 9 Dec 2025). The paper’s main contribution is therefore diagnostic: representation format, geometric inductive bias, and realism of synthetic data materially change behavior, and generic LLM-style models remain unstable on unseen circuit configurations (Esfandiari et al., 9 Dec 2025).
4. Benchmarks, diagnostics, and reliability findings
A defining feature of the LCM literature is that evaluation has shifted from single-score task accuracy toward topology-aware, convention-aware, multimodal, and hierarchical diagnostics. Several benchmark papers now argue that generic reasoning metrics are not sufficient for circuit-capable models.
“CIRCUIT” is an early analog-circuit reasoning benchmark containing 510 question-answer pairs derived from 102 templates with 5 numerical setups per template (Skelic et al., 11 Feb 2025). Its most distinctive idea is the unit-test structure: each topology is instantiated across multiple value assignments, so robustness can be measured by pass@$1000$6 rather than single-instance success. The best reported model, GPT-4o, reaches $1000$7 final-answer accuracy but only $1000$8 unit-test pass rate, and human analysis identifies reasoning errors—especially topology misunderstanding—as the dominant failure mode (Skelic et al., 11 Feb 2025).
“CircuChain” narrows the problem further by distinguishing physical reasoning competence from instruction or convention compliance in linear DC circuit analysis (Ravishankara, 29 Jan 2026). It contains 5 fixed circuit topologies, 50 manually authored problem instances, and two analysis modes—Mesh/KVL and Nodal/KCL—yielding 100 scored subtasks per model. The benchmark introduces counterbalanced Control and Trap conditions and a five-way error taxonomy, then aggregates failures into Compliance Errors and Competence Errors. Across GPT-5, Claude Opus 4.5, o4-mini, GPT-4o, and GPT-4o Mini, the strongest quantitative result is the Compliance–Competence Divergence: GPT-5 attains $1000$9 overall accuracy with $1.85$0 Compliance Error and $1.85$1 Competence Error, while Claude Opus 4.5 attains $1.85$2 overall accuracy with $1.85$3 Compliance Error and $1.85$4 Competence Error (Ravishankara, 29 Jan 2026). The paper names the central failure mode “Convention Blindness,” defined as the tendency of an LLM to override explicit instructions in favor of implicitly learned priors (Ravishankara, 29 Jan 2026).
“CircuitSense” extends benchmarking to multimodal engineering reasoning with 8,006+ problems spanning Perception, Analysis, and Design across six hierarchy levels from resistive networks to system-level block diagrams (Akbari et al., 26 Sep 2025). The headline result is a large gap between visual parsing and symbolic derivation: closed-source models achieve over $1.85$5 accuracy on perception tasks involving component recognition and topology identification, yet performance on synthetic symbolic derivation remains below $1.85$6, with Gemini-2.5-Pro at $1.85$7 overall and most other tested models around $1.85$8–$1.85$9 (Akbari et al., 26 Sep 2025). The benchmark’s interpretation is correspondingly strong: symbolic reasoning, not visual perception, is the decisive metric for engineering competence (Akbari et al., 26 Sep 2025).
“Complexity Horizons of Compressed Models in Analog Circuit Analysis” adds another evaluation axis by representing analog electronics knowledge as prerequisite DAGs and routing queries across compressed model variants according to branchwise failure counts (Mbonimpa, 4 May 2026). Using gemma3:270m, gemma3:1b, and gemma3:4b, the paper defines a model’s “Complexity Horizon” as the point in the hierarchical task graph at which it ceases to succeed as conceptual complexity increases, and argues that flat average accuracy obscures these prerequisite-driven boundaries (Mbonimpa, 4 May 2026).
5. Applications and current practical impact
The survey and panel literature present a broad application map, but they also distinguish sharply between near-term practicality and long-term aspiration. On the encoder side, circuit foundation models are already used for early-stage design quality evaluation, PPA prediction, timing, congestion, wirelength, parasitic capacitance, hotspot estimation, verification-oriented embeddings, and logic- or SAT-related tasks (Fang et al., 28 Mar 2025). On the decoder side, the most active areas are specification-to-RTL generation, HLS generation, assertion and testbench generation, debugging, documentation and report assistance, design-flow scripting, and analog design automation (Fang et al., 28 Mar 2025).
The panel assessment is more skeptical about immediate disruption. It argues that current practical impact is concentrated much more in LLM-adjacent supportive tasks than in fully realized LCM-driven core EDA optimization, and that the strongest demonstrated capabilities today are assistant-style workflows rather than autonomous chip design (Xu et al., 5 Sep 2025). Representative examples include Synopsys Knowledge Assistant, Run Assistant, and Euclide IDE, as well as research systems for RTL generation, verification collateral generation, report understanding, and debugging. In that discussion, hybridization is the central systems principle: LLM or LCM generation should be anchored by simulation, formal verification, waveform tracing, retrieval, or traditional optimization engines rather than replacing them outright (Xu et al., 5 Sep 2025).
The long-term motivation remains stronger than the near-term evidence. The AI-native EDA vision paper explicitly argues that multimodal, cross-abstraction LCMs could enable earlier prediction, earlier debugging, more integrated verification, richer interactive assistance, and a broader “shift-left” in methodology by aligning specification, HLS, RTL, netlist, and layout representations (Chen et al., 2024). The survey reaches a similar conclusion, but in more operational terms: the most promising directions are multimodal circuit fusion, cross-stage alignment, scalable graph transformers, tool-grounded LLM generation, synthetic data generation, and eventual integration of encoder and decoder paradigms (Fang et al., 28 Mar 2025).
6. Limitations, controversies, and research agenda
The central controversy in the LCM literature is whether current progress constitutes a durable foundation-model paradigm for circuits or a collection of promising but still narrow augmentations around existing EDA workflows. The panel paper’s answer is deliberately mixed: there is real opportunity, especially for changing how designers interact with tools and for improving certain generation, understanding, and exploration tasks, but the revolutionary vision for LCMs remains largely aspirational until stronger evidence is available on reliability, scalability, and integration with industrial sign-off flows (Xu et al., 5 Sep 2025).
Data scarcity is repeatedly presented as a structural bottleneck. Open circuit datasets are limited because cutting-edge designs are proprietary, best-in-class layouts and sign-off artifacts are commercially sensitive, and advanced-node examples are scarce; the survey therefore recommends larger multimodal datasets, synthetic data generation, and data augmentation through functionally equivalent transformations (Fang et al., 28 Mar 2025). Representation remains another unresolved issue. The AI-native EDA paper calls for modality-specific encoders plus alignment across design stages, but does not specify a single dominant representation scheme; ACDC then shows empirically that format choice, geometric inductive bias, and synthetic-data realism strongly affect transfer to real analog layout tasks (Chen et al., 2024, Esfandiari et al., 9 Dec 2025).
Reliability problems are no less serious on the reasoning side. CircuChain shows that frontier capability alone is not sufficient because a model can be physically competent yet conventionally noncompliant, a distinction that is operationally significant in engineering settings (Ravishankara, 29 Jan 2026). CircuitLM reaches high structural fidelity in microcontroller-centric designs, but its own limitations list is extensive: a 50-component knowledge base, weak analog and mixed-signal reasoning, no formal netlist stage, no SPICE, no ERC, and validation partly dependent on a single evaluator model (Hasan et al., 8 Jan 2026). More broadly, the panel literature treats hallucinations, non-determinism, numerical weakness, benchmark saturation, and the continuing strength of domain-optimized algorithms as major barriers to replacing classical EDA in sign-off-critical loops (Xu et al., 5 Sep 2025).
The resulting research agenda is increasingly consistent across papers. It includes building EDA-native foundation models from the ground up rather than only adapting generic LLMs, creating larger multimodal corpora spanning specifications to layout, improving graph and multimodal architectures, designing harder and more leakage-resistant benchmarks, coupling generation to formal verification and simulation, and integrating encoder-side circuit embeddings with decoder-side generative systems (Fang et al., 28 Mar 2025). A plausible implication is that mature LCMs will be neither pure LLMs nor single-task graph predictors, but hybrid systems that combine multimodal pre-training, structured circuit representations, tool-in-the-loop checking, and explicit alignment across the design continuum.