GAP9 RISC-V SoC for Edge AI

Updated 23 July 2025

GAP9 RISC-V SoC is a highly integrated computing platform designed for energy-efficient DSP, ML, and AI at the edge.
Its scalable multi-core architecture and on-chip neural accelerator enable real-time signal processing and federated learning.
Deployed in wearables, nano-drones, and medical devices, GAP9 optimizes energy use, latency, and data transmission for embedded applications.

The GAP9 RISC-V System-on-Chip (SoC) is a highly integrated, ultra-low-power computing platform designed for advanced edge applications requiring high-throughput, energy-efficient digital signal processing (DSP), ML, and embedded AI. Leveraging a scalable multi-core RISC-V cluster architecture, configurable memory hierarchy, on-chip neural accelerators, and rich peripheral support, GAP9 targets applications spanning nano-drones, wearable biosignal processing, and federated edge intelligence. Recent research demonstrates GAP9’s deployment in medical-grade biosignal acquisition, on-device continual learning, drone navigation, and heterogeneous IoT systems, with stringent metrics on energy efficiency, latency, and size (Frey et al., 2023, Müller et al., 27 Jun 2024, Kröger et al., 21 Mar 2025).

1. Architecture and Microarchitectural Features

The core of GAP9 comprises a parallel RISC-V processor cluster, typically integrating 9–10 32-bit RISC-V cores within a compact die footprint (3.7 × 3.7 mm² WLCSP reported), complemented by a separate single-core controller. The compute cluster supports high-throughput, multi-precision signal processing and ML workloads through tightly-coupled data memory (TCDM)—up to 128 kB for parallel communication between cores—and shared on-chip memory resources, such as 1.5 MB SRAM and 2 MB flash (Frey et al., 2023, Kröger et al., 21 Mar 2025).

Key features include:

Multi-core Execution: Up to 10 RISC-V cores collaborate on parallel tasks, e.g., pipelined FFT or CNN inference.
Programmable Precision: The architecture and instruction set support aggressive quantization (e.g., 2–16-bit weights, 8–16-bit features) as well as IEEE 32/16-bit and bfloat16 floating-point arithmetic.
Dedicated ML Accelerator (NE16): A hardware convolution and matrix arithmetic engine supports asymmetric, per-layer quantization, boosting ML performance (up to 32.2 GMACs or 150 GOPS aggregate) for convolutional networks and DSP kernels (Frey et al., 2023, Müller et al., 27 Jun 2024).
Dynamic Voltage and Frequency Scaling & Clock Gating: Power consumption is minimized by switching between low-voltage (0.65 V at 240 MHz) and higher-performance (800 mV at 370 MHz) operating modes (Frey et al., 2023, Kröger et al., 21 Mar 2025).
Peripheral Integration: GAP9 platforms typically include interfaces for sensors (SPI, I2C), analog front-ends (AEFs for ExG, PPG), and wireless communication modules (e.g., BLE, WiFi) (Frey et al., 2023, Müller et al., 27 Jun 2024).

In the GAP9Shield module for nano-drones, these hardware elements are tightly integrated with vision (MIPI CSI-2 camera), ranging (VL53L1 time-of-flight array), and wireless (NINA BLE/WiFi) components, directly enabling complex edge perception and navigation (Müller et al., 27 Jun 2024).

2. Software Stack, Programming Model, and Toolchain

GAP9 is supported by a robust software environment comprising:

Compiler Toolchains: RISC-V GCC and LLVM-based toolchains, as well as a tailored build system for efficient DSP/ML code generation and offloading to neural accelerators (Bandara et al., 2019).
Bare-metal and RTOS Support: Lightweight runtimes, explicit memory management for scratchpad/TCDM access, and support for multithreaded execution (OpenMP directives for heterogeneous offloading in comparably architected SoCs) (Valente et al., 2022).
ML and DSP Workflows: Users can define and offload compute-intensive operations, such as GEMM or custom convolution kernels, to either the instruction cores or NE16 via library interfaces. This is exemplified by heterogeneous OpenBLAS acceleration where kernels are mapped from high-level Python (NumPy) down to parallelized execution on the compute cluster in FPGA-emulated systems (Koenig et al., 21 Mar 2025).
Platform Simulation and Verification: Support for RTL simulation and FPGA-based emulation, including cycle-accurate simulators (GVSoC for architectural tradeoff analysis), and FPGA-assisted cross-verification environments (FERIVer) for rapid functional and hardware-accurate testing at speeds up to 5 MIPS (Bruschi et al., 2022, Qin et al., 7 Apr 2025).

The modular construction of the runtime and toolchain enables both rapid prototyping for algorithm exploration and energy/performance profiling for real-world workloads.

3. Application Domains and System Implementations

GAP9 is deployed in a diverse array of embedded AI and edge-computing scenarios that require a confluence of high computational throughput, energy efficiency, and strict size constraints:

Wearable Biosignal Acquisition: In the BioGAP platform, GAP9 processes high-resolution, multi-channel EEG and PPG signals, executing on-board FFT and ML analysis (e.g., SSVEP BCI decoding) at 16.7 Mflops/s/mW—achieving 2.2 μJ/sample energy and reducing wireless data rates by 97% due to local inference (Frey et al., 2023). The modular system comprises GAP9, BLE SoC, AFE (ADS1298), and integrated PPG sensors.
Nano-drones: The GAP9Shield enables energy-constrained platforms (6g, 4050 mm³ module) for drone vision, object detection (YOLO), SLAM, and dynamic obstacle avoidance. Object detection can complete in 17 ms at sub-100 mW system power, with the CPU and NE16 accelerator orchestrating vision pipelines (Müller et al., 27 Jun 2024).
On-device Federated Continual Learning: GAP9’s parallel cluster and quantized NN support enable intelligent nano-drone swarms to perform privacy-preserving local adaptation and distributed global knowledge fusion. A regularization-based Federated Continual Learning algorithm on DSICNet (30k parameters) achieves 24% higher accuracy than naive fine-tuning, with training latencies of 117–178 ms per local epoch and 10.5 s global aggregation via UWB (Kröger et al., 21 Mar 2025).
Edge DSP/ML: GAP9’s support for multi-precision arithmetic and custom accelerator offload allows its deployment in low-power AIoT tasks, medical-grade signal processing, and real-time event analysis (Frey et al., 2023, Müller et al., 27 Jun 2024, Valente et al., 2022).

Below is a table summarizing typical application-specific configurations:

Platform	Application Domain	Compute Cores	NE16 Accelerator	Memory (SRAM + Flash)	Power Envelope	Key Metric
BioGAP	Wearable BCI, EEG	10	Yes	1.5 MB + 2 MB	18.2 mW (<2.2 μJ/sample)	97% raw data bandwidth saved
GAP9Shield	Nano-drone vision	9	Yes	1.6 MB + 2 MB	<100 mW (AI)	17 ms YOLO detection
Nano-drone FL	Federated Learning	10	Yes	1.5 MB + 2 MB	117–178 ms/epoch (4.3 mJ)	24% accuracy gain (FL)

4. Performance and Energy Efficiency

GAP9 platforms achieve high-performance metrics on critical DSP and ML kernels while maintaining ultra-low energy consumption:

Floating-point FFTs: Parallelized computation of eight 1024-point FFTs in 0.425 ms, with per-task energy of 16.7 Mflops/s/mW (Frey et al., 2023).
Neural Inference: ML accelerator performance up to 32.2 GMAC and DSP up to 15.6 GOPS at 370 MHz (Frey et al., 2023, Müller et al., 27 Jun 2024).
Object Detection: End-to-end YOLO detection in 17 ms at system power below 100 mW, with average inference energy between 1.59 and 2.5 mJ per frame (Müller et al., 27 Jun 2024).
Power Gating and Low Sleep: Sleep state power down to 45 μW, dynamic scaling to adapt to application workload (Müller et al., 27 Jun 2024).
Bandwidth Optimization: Local processing reduces wireless data transmission rates by up to 97%, significantly extending battery life and reducing communication cost in distributed IoT and swarm applications (Frey et al., 2023, Kröger et al., 21 Mar 2025).

5. System Integration and Verification

The modularity of GAP9, both at hardware (e.g. TCDM, NE16, standard RISC-V cores) and software (toolchain, libraries), enables efficient system integration and verification workflows:

Rapid Prototyping: Support for synthesizable RTL simulation and FPGA-based emulation allows for real-time bringup of custom systems, as exemplified by the use of GVSoC (Bruschi et al., 2022) and FERIVer frameworks for verification acceleration (up to 5 MIPS, 35–150× faster than traditional toolchains) (Qin et al., 7 Apr 2025).
Incremental Modification: Architecture parameterization (address bits, cache organization, number of cores) and modular interfaces make it feasible to tailor GAP9-based SoCs for specific needs, or to expand with heterogeneous tiles in MPSoC deployments (Bandara et al., 2019, Silva et al., 25 Jun 2024).
Standardized Interconnects: Integration with AXI/AXI-Lite, NoC, and industry-standard peripherals ensures compatibility with external sensors, wireless modules, and other on-chip or off-chip accelerators (Silva et al., 25 Jun 2024).

6. Comparative Analysis and Research Directions

GAP9 participates in a landscape of heterogeneous, ultra-low-power RISC-V SoCs targeting edge intelligence. When compared with analogous platforms, GAP9 is typically noted for:

Compactness and Energy Efficiency: Its WLCSP packaging, sleep power, and total energy per inference or sample are at the forefront for wearable and mobile edge devices (Frey et al., 2023, Müller et al., 27 Jun 2024).
Versatile ML/DSP Support: The NE16 accelerator and flexible multi-precision paths enable both traditional DSP and state-of-the-art ML tasks, including federated continual learning in distributed settings (Kröger et al., 21 Mar 2025).
System Integration: The combination of controller core, compute cluster, scalable memory hierarchy, and ease of peripheral interfacing supports deployment in modular platforms such as BioGAP and GAP9Shield, allowing coherent operation with AFEs, BLE/WiFi, and onboard battery management (Müller et al., 27 Jun 2024, Frey et al., 2023).
Open-Source Ecosystem: Architectures related to CV32E or other open-source RISC-V cores—such as NoX and ESP-based SoC platforms—share similar modular integration strategies, and progress on software stacks (OpenMP, OpenBLAS acceleration) is reflected in GAP9-related workflows (Koenig et al., 21 Mar 2025, Zuckerman et al., 2022, Valente et al., 2022, Silva et al., 25 Jun 2024).

Future research is likely to address further reduction in inference latency and energy, tighter memory hierarchies, richer peripheral integration, and flexibility for on-device learning under resource constraints (as demonstrated by federated learning deployments) (Kröger et al., 21 Mar 2025).

7. Limitations and Design Trade-offs

Design choices in GAP9—including aggressive quantization, use of tightly coupled scratchpad over traditional cache hierarchies, and specialization of the neural accelerator—favor energy efficiency and predictable timing at the cost of reduced flexibility relative to full Linux-capable, general-purpose SoCs (Valente et al., 2022). System complexity is also concentrated in the programming model, demanding explicit management of memory and parallelization. Wireless offloading and federated learning require careful balancing of communication latency, synchronization, and on-device storage. A plausible implication is that such architectures are best suited to domain-specific, IoT-scale workloads with well-characterized compute and memory footprints, rather than as drop-in replacements for all-purpose embedded systems.

In summary, the GAP9 RISC-V System-on-Chip exemplifies advanced design for edge AI, DSP, and intelligent autonomous platforms, supporting stringent energy, size, and real-time constraints. Its modular, cluster-oriented architecture, on-chip neural accelerator, and support for federated edge intelligence situate it as a leading choice in wearable bio-informatics, nano-drone navigation, and distributed AI sensor networks (Frey et al., 2023, Müller et al., 27 Jun 2024, Kröger et al., 21 Mar 2025).