RTL Code Generation Advances
- RTL code generation is the automated synthesis of Verilog and VHDL code defining digital systems using registers, combinational logic, and clocked data transfers.
- Modern methodologies employ multi-stage pipelines, retrieval-augmented techniques, and syntax-aware decoding to achieve cycle-accurate, functionally correct designs.
- Key challenges include managing strict bit-width discipline, multi-file hierarchies, and equivalence verification between software models and hardware implementations.
Register Transfer Level (RTL) code generation is the task of synthesizing hardware description language code—typically Verilog or VHDL—that specifies digital systems in terms of registers, combinational logic, and clocked data transfers. In contemporary work, the task appears in several forms: natural-language-to-RTL synthesis, repository-level completion, refactoring, debugging, and formally verified generation from executable reference models. What makes RTL code generation distinctive is that it must preserve both syntactic validity and functional correctness under cycle-accurate, concurrent semantics: structurally different code can still implement the same hardware, while small syntactic changes such as blocking versus non-blocking assignment or operator-precedence differences can drastically alter behavior (Mashnoor et al., 22 Oct 2025, Zuo et al., 29 Apr 2025).
1. Task definitions and design constraints
A central formulation treats RTL generation as autoregressive HDL emission conditioned on a specification. In one widely used setting, the input is a natural-language design description plus a module header, and the output is a Verilog module that compiles and passes verification (Huang et al., 2024). Other work broadens the task to repository-level completion, where the model must predict the next line in a file by conditioning on both repository context and incomplete file context , formalized as (Wu et al., 11 Apr 2025). At the datapath end of the spectrum, FormalRTL defines RTL generation as transforming a C or C++ reference model plus a textual spec into Verilog RTL that is structurally realistic and formally proven equivalent to the software implementation by a C-to-RTL equivalence checker (Li et al., 25 Feb 2026).
The design constraints reported across the literature are unusually stringent. RTL must respect bit-width discipline, clear module interfaces, synchronous resets, hierarchy, and timing behavior; practical tasks involve pipelines, finite-state machines, arithmetic datapaths, protocol logic, and strict port consistency across modules and files (Zuo et al., 29 Apr 2025, Wu et al., 11 Apr 2025). Real projects also exceed the assumptions of single-module generation: repositories may contain multi-file hierarchies, shared parameter files, testbenches, and protocol-specific conventions, and mismatched widths or directions typically cause immediate synthesis or elaboration failure (Wu et al., 11 Apr 2025). Zero-shot, single-prompt generation has been demonstrated for a non-trivial NPU coprocessor, but the reported failure modes—hallucinated signals, corrupt long outputs, port drift, and loss of early prompt constraints—show how strongly RTL stresses long-context attention and structural consistency (Sandal et al., 2024).
2. Benchmarks, corpora, and annotation regimes
The reported datasets span single-module evaluation, repository-scale completion, complex multi-level hierarchy, and large supervised corpora validated for functionality or synthesis.
| Resource | Primary focus | Reported scale or property |
|---|---|---|
| RTL-Repo | Repository-level next-line completion | 4,098 samples from 1,361 open-source Verilog repos; context lengths 2k–128k (Wu et al., 11 Apr 2025) |
| ComplexVDB | Complex Verilog generation | 55 cases; average 151 LOC; hierarchy depth 3 (Zuo et al., 29 Apr 2025) |
| VeriCoder dataset | Functionally validated NL–RTL supervision | 125,777 examples, each with natural language spec, RTL, and passing tests (Wei et al., 22 Apr 2025) |
| DeepCircuitX | Repository/file/module/block corpus with PPA labels | >4,000 repositories, ~140,000 RTL files, 77 categories, synthesized netlists and PPA metrics (Li et al., 25 Feb 2025) |
Benchmarking practice is anchored by VerilogEval and RTLLM. VeriAssist reports 156 tasks for VerilogEval-Human, 143 tasks for VerilogEval-Machine, and 29 RTLLM designs spanning arithmetic and logic/control modules (Huang et al., 2024). ComplexVCoder supplements these with Problem-Set-VeriGen and a new benchmark, ComplexVDB, specifically to move beyond the small, mostly single-level settings in which VerilogEval-Human averages 22 LOC, Problem-Set-VeriGen averages 23 LOC, and RTLLM averages 73 LOC, all with hierarchy depth 1, whereas ComplexVDB averages 151 LOC with hierarchy depth 3 (Zuo et al., 29 Apr 2025).
Several datasets are designed to improve supervision quality rather than just scale. VeriCoder constructs a functionally validated corpus by prompting GPT-4o-mini to generate unit tests, iteratively revise RTL according to simulation results, and, when necessary, revise the tests themselves so they remain aligned with the natural-language specification; only triples that pass simulation are retained (Wei et al., 22 Apr 2025). DeepCircuitX instead organizes RTL at repository, file, module, and block level, and enriches the code with Chain of Thought annotations describing functionality and structure at multiple levels, while also attaching synthesized netlists and PPA metrics for downstream analysis (Li et al., 25 Feb 2025). OriGen takes another route: it starts from open-source Verilog, filters modules by structural and length constraints, removes comments, uses Claude3-Haiku to generate high-level descriptions and regenerated RTL, and then verifies or repairs the regenerated code with Icarus Verilog to build a higher-quality open-source training set (Cui et al., 2024).
3. Generation architectures and inference-time strategies
A major methodological line decomposes generation into explicit intermediate representations or planning stages. ComplexVCoder replaces direct mapping with a two-stage pipeline , where GIR is a JSON-like, hierarchical representation containing modules, parameters, ports, instances, connections, and module-level functional summaries (Zuo et al., 29 Apr 2025). FormalRTL similarly rejects natural-language-only planning: its planning agent uses a Clang AST to extract function dependencies from a C reference model, topologically orders submodules, and drives bottom-up synthesis and equivalence checking with generated verification harnesses (Li et al., 25 Feb 2026). RTLSquad distributes exploration, implementation, and verification across specialized agent squads, with explicit communication and decision paths intended to expose the rationale behind each RTL design choice (Wang et al., 6 Jan 2025).
A second line addresses long context and reuse through retrieval. RTLRepoCoder combines domain-specific fine-tuning of DeepSeek-Coder-Instruct-6.7B with conditional RAG for repository-level next-line prediction; if plus fits within a 10,240-token window it is passed directly, otherwise the system retrieves relevant cross-file snippets, with line-break splitting and long-context embeddings proving superior to shorter embedding models (Wu et al., 11 Apr 2025). DeepV generalizes this into a model-agnostic RAG framework built on VerilogDB, a 20,392-module knowledge base validated with Icarus Verilog and Yosys; it retrieves semantically similar examples with Sentence-Transformers embeddings, FAISS search, a relevance threshold, and a dynamic sampling rule that stops when relevance drops too sharply (Ibnat et al., 6 Oct 2025). Earlier work on attention sinks attacks the same bottleneck at the decoding level by keeping the initial prompt permanently available in the KV cache, so that long single-prompt generation retains access to the original NPU specification, ports, and design guidelines throughout the generation of thousands of tokens (Sandal et al., 2024).
A third line alters inference itself rather than the training data. DecoRTL studies token-level entropy during RTL generation and argues that structural and semantic regions should be decoded differently; it combines self-consistency sampling with a syntax-aware temperature schedule that lowers temperature for syntax-critical tokens such as module, endmodule, always, begin, end, delimiters, and brackets, while allowing higher temperature in design-critical regions such as arithmetic and logical operators (Akyash et al., 3 Jul 2025). MeltRTL treats correctness as a representation-steering problem: it trains lightweight probes on frozen QwenCoder2.5-14B activations, identifies correctness-critical attention heads for combinational, sequential/datapath, and FSM categories, and applies expert-specific inference-time intervention without fine-tuning the base model (Mashnoor et al., 19 Jan 2026). CASS-RTL likewise works at inference time, but its steering variable is a low-dimensional correctness-aware subspace built from attention heads whose EOS-token activation patterns separate correct from incorrect RTL more strongly than two stylistically different correct solutions (Akyash et al., 4 Jun 2026). Search-based decoding has also been applied directly: “Make Every Move Count” formulates token generation as a Markov Decision Process and uses Monte Carlo tree search guided by compiler, simulation, and synthesis rewards, while REvolution evolves a population of designs with dual Fail and Success groups, prompt operators such as Fix, Explore, Refactor, Improve, and Fusion, and an adaptive prompt-selection mechanism based on UCB-style rewards (DeLorenzo et al., 2024, Min et al., 24 Oct 2025).
4. Verification, correctness metrics, and empirical performance
The dominant evaluation distinction is between syntactic validity and functional correctness, and multiple papers argue that syntax is a weak proxy for behavior. VeriCoder reports that on RTLLM, GPT-4o reaches 100% syntax accuracy but only 69% functional correctness at Pass@5; the same paper also tests prior datasets with generated unit tests and finds that, on 1,000 sampled examples, RTLCoder data passes at only 24.4% and OriGen data at 53.5% (Wei et al., 22 Apr 2025). VeriAssist operationalizes this gap with a simulator-in-the-loop workflow: it generates initial RTL and testbenches, performs self-verification by walking through code behavior at different time steps, compiles with Icarus Verilog, and then uses compiler or simulation logs to drive self-correction (Huang et al., 2024). EstRTL adds a static functional estimation layer between generation and correction: it reverse-generates requirements from RTL, compares them to the original specification using token-level and sentence-level semantic similarity plus a completeness score, and routes code either to output, regeneration, or correction according to a functional score threshold (Xiong et al., 1 Jun 2026).
The major task families use different metrics. VerilogEval, RTLLM, ComplexVDB, and Problem-Set-VeriGen are typically reported with pass@k based on compilation plus functional verification (Huang et al., 2024, Zuo et al., 29 Apr 2025). RTLRepoCoder instead uses Edit Similarity and Exact Match for next-line prediction, together with repository-scale context lengths and retrieval ablations (Wu et al., 11 Apr 2025). CircuitGuard introduces an RTL-aware semantic similarity metric for IP leakage, based on concatenated semantic, AST, circuit, connectivity, timing, pattern, operator, lexical, and graph features, and measures leakage as cosine similarity in this weighted feature space (Mashnoor et al., 22 Oct 2025).
Reported results show broad but uneven progress. RTLRepoCoder reaches Edit Similarity 84.3 and Exact Match 55.8 on RTL-Repo, surpassing GPT-4, which is reported at 71.9 and 48.5 on a 200-case subset (Wu et al., 11 Apr 2025). On ComplexVDB, ComplexVCoder with DeepSeek-V3 reports pass@1 and pass@5 , compared with CodeV at pass@1 and RTLCoder at 0 (Zuo et al., 29 Apr 2025). OriGen reports pass@1 1 on VerilogEval-Human and 2 on VerilogEval-Machine, while also introducing VerilogFixEval, where its syntactic correctness reaches 3 pass@1 (Cui et al., 2024). MeltRTL improves QwenCoder2.5-14B from 85.33% synthesizability and 45.33% functional correctness to 96.00% and 60.00% in multi-expert mode, entirely at inference time (Mashnoor et al., 19 Jan 2026). CASS-RTL reports 10%–20% improvement in pass@1/5/10 on VerilogEval and 5% improvement on CVDP across multiple models (Akyash et al., 4 Jun 2026). REvolution pushes DeepSeek-V3 to a final pass rate of 95.5% on VerilogEval, and EstRTL reports correctness gains of 3.2%–9.0% for generic LLMs by inserting estimation-guided correction into the loop (Min et al., 24 Oct 2025, Xiong et al., 1 Jun 2026).
5. Repository-scale reasoning, PPA, and formal guarantees
A persistent theme is that practical RTL generation is not just a module-synthesis problem. Repository-level work emphasizes cross-file dependencies, interface consistency, and long-context reasoning. RTLRepoCoder explicitly argues that real hardware development involves large Verilog repositories, shared parameter files, interface definitions, and naming conventions that exceed short context windows, and it shows that both larger fine-tuning context and RAG matter for completion quality (Wu et al., 11 Apr 2025). DeepCircuitX extends this repository view into a data resource that spans repository, file, module, and block levels, and augments RTL with synthesized netlists, AIGs, ASTs, CDFGs, and PPA metrics, thereby enabling early-stage design exploration and PPA prediction directly from RTL (Li et al., 25 Feb 2025).
Power, performance, and area enter the literature in several distinct ways. “Make Every Move Count” incorporates a reward based on compilation, functional correctness, and normalized area-delay product, and reports a 31.8% improvement in the area-delay product of a 16-bit adder relative to the state-of-the-art LLM baseline for that design (DeLorenzo et al., 2024). REvolution treats functionally correct individuals as candidates for PPA optimization and evaluates fitness with weighted improvements in power, area, and effective clock period; on VerilogEval and RTLLM it reports substantial reductions relative to reference designs while also raising final pass rates (Min et al., 24 Oct 2025). RTLSquad uses a verification and evaluation squad to parse synthesis reports, rate exploration plans, and regulate how aggressively the exploration squad pursues PPA changes; it reports matching or exceeding the PPA of the reference design in most cases (73.3%) (Wang et al., 6 Jan 2025).
At the opposite end, FormalRTL makes formal equivalence, rather than PPA, the primary objective. It treats the software reference model as the golden specification, generates a harness that ties C and RTL together, and uses hw-cbmc for bottom-up C-to-RTL equivalence checking; on industrial-style FP16 and HiFloat8 datapath blocks it reports high final success rates for many submodules, while also noting that the resulting RTL is functionally correct but less optimized, with about 30–40% more area and higher delay than engineer-optimized baselines in the reported QoR comparisons (Li et al., 25 Feb 2026). A plausible implication is that the field is splitting into frameworks that prioritize verified functional signoff and frameworks that prioritize broader search over microarchitectures and QoR.
6. IP leakage, safety, and open research directions
RTL code generation raises a safety problem that is specific to hardware IP. CircuitGuard studies memorization in a setting where a LLaMA 3.1–8B-style model is fine-tuned on approximately 1,700 non-sensitive RTL modules and approximately 300 proprietary-marked modules, and defines leakage not only as verbatim copying but also as structural similarity and functional equivalence to proprietary designs (Mashnoor et al., 22 Oct 2025). Its RTL-aware similarity metric aggregates semantic code embeddings, AST features, circuit-level structure, connectivity, timing and control features, design patterns, operator counts, lexical traits, and graph features. On the defense side, it trains sparse autoencoders over layers 18–28, identifies 275 memorization-critical features—about 0.15% of all SAE features, concentrated in deeper layers—and suppresses them during inference, achieving up to 80% reduction in semantic similarity to proprietary patterns with 78–85% cross-domain transfer effectiveness (Mashnoor et al., 22 Oct 2025).
The limitations reported across the field are consistent. Several systems still rely on simulation and testbenches rather than formal guarantees, so passing tests does not imply equivalence to the intended behavior (Huang et al., 2024, Wei et al., 22 Apr 2025). ComplexVCoder notes that errors in the intermediate GIR propagate downstream and that rare or novel architectures may lack good retrieval hits (Zuo et al., 29 Apr 2025). DeepV depends on the quality and coverage of its knowledge base, and its own discussion points to hardware-aware retrieval and richer structural similarity as future directions (Ibnat et al., 6 Oct 2025). CircuitGuard reduces similarity but explicitly does not provide a formal leakage guarantee, depends on knowing which designs are proprietary, and requires fine-grained access to model activations (Mashnoor et al., 22 Oct 2025). FormalRTL, despite formal guarantees for C-backed datapath blocks, leaves control-heavy systems, broader SystemVerilog support, and larger industrial IP as open challenges (Li et al., 25 Feb 2026). EstRTL provides a graded, interpretable functional score, but its static estimation remains a heuristic rather than a proof of correctness (Xiong et al., 1 Jun 2026).
Across these results, a recurrent misconception is that “better RTL generation” can be read off from surface-level code quality or from single-module benchmarks alone. The evidence instead points to a more demanding picture: syntax accuracy can coexist with poor functional correctness; single-pass prompting can be outperformed by retrieval, self-correction, search, or steering; and strong functional results do not by themselves resolve PPA, IP leakage, or formal signoff. This suggests that RTL code generation is evolving from a code-synthesis problem into a layered design automation problem that combines specification handling, hierarchical context, retrieval, verification, optimization, and model-internal control (Wei et al., 22 Apr 2025, Min et al., 24 Oct 2025, Li et al., 25 Feb 2026).