AnalogCoder-Pro: Unified Analog Circuit Synthesis

• AnalogCoder-Pro is a unified multimodal framework for analog circuit synthesis that integrates LLMs, MLLMs, and Bayesian optimization to jointly optimize topology and device sizing.
• It employs advanced methods like rejection sampling fine-tuning and multi-resolution bias search to enhance design reliability and performance metrics.
• The framework streamlines the analog design workflow by automating netlist generation, simulation verification, and multimodal diagnostics for accurate circuit performance.

AnalogCoder-Pro is a unified multimodal framework for analog circuit synthesis and optimization, integrating LLMs, multimodal LLMs (MLLMs) for waveform interpretation, and advanced search/optimization methods. Its design addresses end-to-end automation for analog front-end circuits, coupling topology generation with device sizing to meet stringent performance targets without human-in-the-loop iteration. By fusing functionally verified data, rejection sampling, multimodal diagnostics, and closed-loop Bayesian optimization, AnalogCoder-Pro achieves performance and automation levels previously unattainable in analog design workflows (Lai et al., 4 Aug 2025).

1. Motivation and Background

Analog front-end design traditionally consists of two decoupled steps: (i) topology exploration (selecting circuit architectures, e.g., amplifiers, filters) and (ii) device sizing (tuning parameters—transistor $W/L$, $R$, $C$, bias voltages—to optimize metrics such as gain, bandwidth, and power). This partitioned flow is brittle, as a promising topology may not be tunable to specification and typically requires extensive human insight and numerous SPICE simulations. Existing LLM-based tools for analog circuit design, such as AnalogCoder, automate parts of this process via code generation and self-correcting flows (Lai et al., 2024), but lack joint, performance-driven co-design and deep integration of optimization and multimodal feedback.

AnalogCoder-Pro is motivated by the premise that topology and sizing are inextricably linked and must be optimized together. The approach leverages advances in LLM and MLLM technology, together with systematic function-checking, dataset curation, and classical optimization, to systematize analog design from high-level specification to final netlist and verified performance.

2. Model Architecture and Training Paradigms

AnalogCoder-Pro’s pipeline consists of intertwined generative and diagnostic modules:

• Circuit Generation uses a fine-tuned LLM (e.g., Qwen2.5-Coder [LoRA-adapted]) to produce SPICE netlists from functional specifications.
• Multimodal Debugging incorporates a pretrained visual encoder (e.g., ViT), extracting learned feature embeddings from waveform images ($$z_\mathrm{vision} = E_\mathrm{vision}(I_\mathrm{waveform})$$), fused with textual netlist embeddings ($$z_\mathrm{text} = E_\mathrm{text}(T_\mathrm{netlist})$$) in a shared Transformer decoder.
• Optimization-Driven Sizing applies Bayesian optimization (BO) with surrogate models (typically TPE), leveraging LLM-parsed netlists to extract optimization variables, suggest bounds, and decouple bias conditions via multi-resolution search (e.g., $$v_\mathrm{in}^* = \operatorname{argmin}_v |v_\mathrm{out}(v) - V_\mathrm{DD}/2|$$).

Data quality is ensured by Rejection Sampling Fine-Tuning (RSFT): Only functionally verified netlists—generated by the framework, simulated under built-in tests (DC, AC, transient), and passing functional metrics—are retained as training data. This process yielded, for example, 390 verified amplifier netlists from 153 template descriptions, ensuring high sampling efficiency and model reliability (Lai et al., 4 Aug 2025).

3. End-to-End Workflow and Core Methodologies

AnalogCoder-Pro operates via three tightly integrated modules:

1. RSFT Dataset Generation:
   • MLLM extracts circuit descriptions and types from schematics.
   • LLM generates $k$ candidate netlists per description.
   • Each netlist is simulated and tested; only those passing all specification checks are retained.
   • Verified (prompt $\rightarrow$ netlist) pairs comprise the dataset for fine-tuning.
2. MLLM-Driven Topology Debug:
   • Functionally incorrect or marginal netlists are debugged by analyzing generated waveform images with the MLLM, yielding diagnostic explanations (e.g., "gain peaking at 50 MHz").
   • Diagnostics are fed back to the LLM to trigger topological or parameter modifications (e.g., bias adjustments, compensation changes).
   • Up to two additional feedback iterations are used to improve Pass@1 success.
3. LLM-Assisted Parameter Extraction and Sizing:
   • From a syntactically and functionally validated netlist, the LLM parses tunable design variables and bounds.
   • Multi-resolution search identifies optimal biasing, constraining BO to a physically valid subspace.
   • Bayesian optimization maximizes a user-defined figure-of-merit (e.g., $\mathrm{GBW}\cdot C_L/\mathrm{Power}$) within prescribed parameter bounds.

This unified loop collapses traditional partitioned flows, permitting simultaneous exploration and sizing; the system generates netlists that are more likely to be directly optimizable to the user’s specification.

4. Experimental Results and Evaluation Metrics

AnalogCoder-Pro was benchmarked on 30 design tasks across 15 circuit types (amplifiers, filters, comparators, oscillators, etc.). Key performance metrics include:

• Pass@1: Probability that at least one out of $n$ generated netlists meets all functional requirements after up to two feedback rounds.
• Sizing Quality: Maximum $R$0 achieved for each design (e.g., $R$1).

Results indicate:

• RSFT delivers a $R$210–17 percentage point improvement in Pass@1 over standard fine-tuning, depending on model scale.
• MLLM Debugging increases debugging success by 7 points for Qwen2.5 and 6 points for Claude-3.7; systematic improvement is observed in diagnosing complex failure modes (e.g., unintended oscillation, spectral peaking).
• Unified Generation + Optimization: Up to 2$R$3 improvement in $R$4 compared to prior frameworks for two-stage op-amp synthesis. For single-stage amplifiers, median performance achieves gain $R$5, $R$6, $R$7.
• Multi-Resolution Bias Search shows %%%%18$$z_\mathrm{vision} = E_\mathrm{vision}(I_\mathrm{waveform})$$19%%%% faster convergence and $C$010% higher $C$1 than fixed- or single-resolution searches.

A comparative summary is provided:

Method	Topology Pass@1	Sizing Median FoM	MLLM Debug Success
Qwen2.5 (base)	26.2%	—	17.5%
RSFT (Qwen2.5-32B)	30.6%	—	24.6%
Claude-3.7 + MLLM	84.1% → 90.2%	>120 MHz·pF/μW	+6.1%
Human reference(45 nm)	—	60–80 MHz·pF/μW	—

All performance claims strictly reflect empirically measured data and pipeline logic from (Lai et al., 4 Aug 2025).

5. Comparisons with Predecessor and Related Approaches

AnalogCoder-Pro supersedes earlier LLM-analog design frameworks in several dimensions:

• Automation and Integration: Unlike AnalogCoder (Lai et al., 2024), which wraps code generation with simulation-based error correction and a tool library for reuse, AnalogCoder-Pro performs joint generation and optimization, incorporates visual (waveform) information, and introduces verification-driven data curation.
• Optimization Capabilities: Whereas prior methods may rely on functional correctness alone, AnalogCoder-Pro embeds classical optimizers (Bayesian, multi-resolution searches) and parses netlist parameter spaces for systematic performance targeting.
• Data Quality: AnalogCoder-Pro’s RSFT removes low-quality, nonfunctional netlists, counteracting a major source of inefficiency and model drift, especially when dataset scale is limited.
• Multimodality: MLLM integration achieves significant improvement in diagnosing failure cases, particularly those evident in spectral or time-domain visualizations.

A plausible implication is that as analog circuits increase in complexity or specification tightness, analog design automation will increasingly require such a closed-loop, data-driven, and multimodal approach.

6. Limitations, Open Challenges, and Future Directions

Current limitations of AnalogCoder-Pro include:

• Scalability: Experiments focus on small-to-medium analog blocks; extension to large-scale systems (full ADCs, PLLs) will increase netlist size, testbench complexity, and simulation overhead.
• Layout Integration: Translating parameter-optimized netlists into layout-aware, parasitic-inclusive implementations remains an open area, as does GDS-level physical design automation.
• Domain Adaptation: Portability across process nodes (e.g., migration from bulk CMOS to FinFET) necessitates regeneration of verified data with updated parameter bounds. Active learning, on-the-fly SPICE tuning, or simulation-in-the-loop may mitigate this bottleneck.
• Computational Cost: MLLM-based waveform reasoning incurs higher latency and compute demands compared to text-only approaches; deployment in industry contexts may require further optimization or specialized accelerators.

Future research may pursue active integration of layout synthesis, domain adaptation via continual learning, and scalable multimodal architectures for even larger circuit classes.

7. Foundations in Analog Coding and Online A/D Conversion

AnalogCoder-Pro’s architectural approach is informed by foundational work in robust analog encoding and coding against noise:

• Algorithmic Encoders and Robustness: Principles from the Golden-Ratio Encoder (GRE) demonstrate that bounded-state, low-precision analog arithmetic with robust invariant-set design enables exponential accuracy under wide hardware perturbations. These principles (β-representation, polytopic invariance, and higher-order generalizations) inform the foundation for robust, high-performance analog coders (0809.1257).
• Few-Shot, Channel-Agnostic Coding: Near-optimal, SNR-agnostic analog transmission is achieved by progressive expansion, cyclic digit distribution, and noise-shielding mechanisms that attain $C$2 within $C$3 of optimal for all channel states (Maddah-Ali et al., 2024).
• Online Coding for Analog Signals: Linear, causal encoders operating as memory-efficient filter banks provide real-time, power-preserving $C$4-guaranteed coding against adversarial noise, with error decaying as $C$5 for streaming sources (Schulman et al., 2017).

This suggests that hardware-aware algorithmic invariants and time-causal designs from analog coding theory underpin the robustness and reliability sought in LLM-driven analog CAD tools.

---

References:

• "AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs" (Lai et al., 4 Aug 2025)
• "AnalogCoder: Analog Circuit Design via Training-Free Code Generation" (Lai et al., 2024)
• "The Golden Ratio Encoder" (0809.1257)
• "Few-Shot Channel-Agnostic Analog Coding: A Near-Optimal Scheme" (Maddah-Ali et al., 2024)
• "Online codes for analog signals" (Schulman et al., 2017)