Modulo ADC: Extended Range & Recovery

• Modulo ADCs are quantization systems that apply a folding operator to confine signals within a fixed amplitude range, thereby extending dynamic range.
• They employ diverse analog front-end architectures, such as comb-generator with low-pass filtering and FPGA-controlled feedback, to mitigate high-frequency artifacts.
• Digital unfolding algorithms reconstruct the original signal by recovering integer fold counts using techniques like projected gradient descent and adaptive prediction.

A modulo analog-to-digital converter (ADC) is a quantization architecture that extends the effective dynamic range of ADCs by performing a modulo (or self-reset/folding) operation on the input signal prior to quantization. This operation preserves information about the original analog signal over an unbounded amplitude range by folding the signal into a channel with restricted amplitude, enabling reliable sampling and recovery even when the actual signal amplitude exceeds the ADC’s nominal range. Modulo ADCs can achieve substantial improvements in dynamic range, bit efficiency, and robustness to out-of-range signals across various signal classes—including bandlimited, shift-invariant, and finite-rate-of-innovation (FRI) signals—while supporting contemporary hardware realizations in both discrete and integrated analog-digital platforms.

1. Mathematical Model and Modulo Folding Principle

The core principle of the modulo ADC is the application of a folding operator to the input analog signal before quantization. For an amplitude parameter $\lambda>0$, the centered modulo operator is typically defined as

$$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$

such that the output $s(t) = \mathcal{M}_\lambda\{x\}(t)$ is always confined to $[-\lambda, \lambda]$ regardless of the amplitude of $x(t)$. In discrete time, upon sampling at periods $T_s$, this yields

$y[n] = \mathcal{M}_\lambda\{x\}(nT_s).$

This folding preserves the necessary information for reconstructing the original signal up to integer-valued fold counts; the recovery problem becomes that of determining the sequence of integer modulo offsets from the observed folded sequence.

A direct consequence of the modulo operation is that although the original input $x(t)$ may be bandlimited, $s(t)$ (the modulo-folded signal) is not: the nonlinear folding introduces high-frequency "spikes" in the frequency domain $S(\omega) = \mathcal{F}\{s\}(\omega)$, which must be addressed in practical hardware to avoid signal distortion in subsequent quantization and recovery (Kvich et al., 20 Jan 2025).

2. Analog Front-End Architectures and Practical Realizations

Several hardware realizations of modulo ADCs have been demonstrated:

• Comb-Generator + Low-Pass Filter (LPF) Front End: To address the high-frequency artifacts introduced by the modulo operation, the analog folded signal $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$0 is mixed with a $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$1-periodic pulse train (comb), and then passed through a LPF with cutoff frequency $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$2. The effect is to suppress out-of-band spectral spikes while preserving the baseband content necessary for ideal recovery (Kvich et al., 20 Jan 2025). After sampling, the resulting sequence

$$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$3

is mathematically equivalent to the output of an ideal wideband modulo ADC, enabling use of all established modulo recovery algorithms.

• Feedback-Controlled (FPGA or MCU) Modulo ADC: Realized with an analog front end for thresholding, high-speed window comparators, and a digital feedback loop (FPGA, MCU, or logic) that maintains the fold count and generates the appropriate feedback voltage for folding, modern systems can achieve dynamic-range expansion beyond two orders of magnitude (over $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$4) with real-time unfolding (Li et al., 27 Nov 2025, Zhu et al., 2024).
• Pure Analog Schmitt-Trigger/Integrator-Based Design: The “integrator-based modulo ADC” introduces a continuous analog feedback mechanism, using an op-amp-based integrator loop to reset the output each time the folded signal exceeds $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$5, supporting high folding rates unconstrained by digital logic speed, enabling $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$6 or greater dynamic range with up to $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$7 ENOB and SINAD improvements up to $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$8 dB (Zhu et al., 2024).

These architectures can be realized with standard analog and mixed-signal parts, as demonstrated in real-time prototypes that mitigate or eliminate clipping and achieve high signal fidelity over large amplitude ranges.

3. Digital Unfolding and Recovery Algorithms

The main challenge in modulo ADCs is robust and computationally efficient recovery (unfolding) of the original signal from quantized, folded samples:

• Residual Recovery (B²R², LASSO-B²R², etc.): State-of-the-art algorithms pose the unwrapping problem as reconstructing the sparse, integer-valued "residuals" $$\mathcal{M}_\lambda\{x\}(t) = \bigl(x(t) + \lambda\bigr)\bmod 2\lambda - \lambda,$$9 added by the folding. B²R² formulates this in the frequency domain: exploiting the known Fourier support of the bandlimited signal, it isolates the residuals via projected gradient descent or, in the presence of 1-bit folding side information, via direct pseudo-inverse (least-squares) computation (Azar et al., 2021, Shah et al., 2024).
• Blind Predictive and Adaptive Approaches: Blind modulo ADCs use adaptive prediction filters (e.g., LMS) to recursively estimate and unwrap the sequence without prior signal statistics. Robustified versions (e.g., AMAP detector) can tolerate large prediction errors and integer ambiguities by online estimation of the integer wrap index via maximum a posteriori rule (Weiss, 2024, Weiss et al., 2021, Weiss et al., 2021).
• Sliding-DFT and Spectral Methods (1-bit Side Information): Efficient recovery using sliding DFT windows with 1-bit folding indicators can perform real-time unfolding with guaranteed mean-square-error bounds, allowing the use of modulo ADCs to surpass the MSE performance of conventional ADCs at moderate oversampling and bit-depth (Bernardo, 2024, Bernardo et al., 2 Jan 2025).
• Line Spectral and FRI Recovery: For FRI and multitone signals, dedicated algorithms (e.g., USLSE) and first-difference (Itoh) methods are used for accurate parameter estimation under tight oversampling factors (Zhu et al., 2024, Mulleti et al., 2022).

With sufficiently low quantization noise and adequate oversampling (typically $s(t) = \mathcal{M}_\lambda\{x\}(t)$0–$s(t) = \mathcal{M}_\lambda\{x\}(t)$1), these methods achieve almost cubic improvements in in-band MSE per oversampling unit, outperforming conventional ADCs whose in-band noise scales only linearly with oversampling (Bernardo et al., 2 Jan 2025).

4. Performance Guarantees: Dynamic Range, Error Rates, and Bit Efficiency

Modulo ADCs provide strong theoretical and empirical guarantees:

• Dynamic Range Expansion: The dynamic range achievable with modulo folding is unbounded in principle; practical systems routinely achieve $s(t) = \mathcal{M}_\lambda\{x\}(t)$2–$s(t) = \mathcal{M}_\lambda\{x\}(t)$3 range extensions over classical ADCs (Li et al., 27 Nov 2025, Zhu et al., 2024, Mulleti et al., 2023).
• Quantization Noise and SNR: For a folded interval of size $s(t) = \mathcal{M}_\lambda\{x\}(t)$4 quantized to $s(t) = \mathcal{M}_\lambda\{x\}(t)$5 bits, quantization noise is minimized in the unfolded signal since only the low-amplitude interval is quantized. The output SNR is independent of the full-scale input amplitude, decoupling amplitude and resolution (Zhu et al., 2024, Liu et al., 2022, Krishna et al., 2019).
• Bit-Rate Efficiency: Two-channel modulo ADC architectures using integer-difference quantization exploit the structure of folding indices to reduce required throughput to just $s(t) = \mathcal{M}_\lambda\{x\}(t)$6–$s(t) = \mathcal{M}_\lambda\{x\}(t)$7 bits/sample overhead relative to conventional ADCs, even under very large dynamic ranges (Yan et al., 20 Jan 2026).
• Error Scalings and Oversampling: With $s(t) = \mathcal{M}_\lambda\{x\}(t)$8 bits and oversampling factor $s(t) = \mathcal{M}_\lambda\{x\}(t)$9, modulo ADCs without (and with) 1-bit folding information achieve MSEs scaling as $[-\lambda, \lambda]$0; this cubic gain in $[-\lambda, \lambda]$1 far exceeds the $[-\lambda, \lambda]$2 of the classical case (Bernardo et al., 2 Jan 2025, Shah et al., 2024).
• Robustness to Hardware Imperfections: Design guidelines recommend sufficient comb harmonics to suppress aliasing, high-order LPF for HF attenuation, precise comparator thresholds, and under-compensated feedback to correct for analog imperfections and prevent drift (Kvich et al., 20 Jan 2025, Li et al., 27 Nov 2025).

Performance is validated by both simulation and hardware, with empirical SNR, ENOB, and MSE matching theoretical predictions in high-precision and extreme-DR settings.

5. Applications, Extensions, and Signal Classes

Modulo ADCs are applicable to a broad spectrum of acquisition and sensing tasks:

• HDR and Sub-Nyquist Sampling: Protoypes demonstrate effective HDR capture ($[-\lambda, \lambda]$3 or more dynamic range) at sub-Nyquist rates for FRI signals (2L+1 samples for $[-\lambda, \lambda]$4 Diracs), with robust unfolding and parameter recovery (Mulleti et al., 2023, Mulleti et al., 2022).
• Vector and MIMO Acquisition: Blind modulo ADCs adaptively learn spatio-temporal signal structure in multi-channel or MIMO settings, requiring neither prior knowledge nor analog mixing, and achieving near-Shannon limit rate-distortion trade-offs (Weiss et al., 2021, Liu et al., 2022).
• SI and Non-Bandlimited Inputs: Modulo sampling strategies extend to shift-invariant spaces via analog preprocessing (mixer + LPF), and can be stabilized against generator zeros using carefully selected mixers (Kvich et al., 2024).
• Bitrate-Constrained and Energy-Efficient Designs: Bit-efficient architectures (e.g., ECRT) and power-optimized FPGA/Mixed-Signal implementations make modulo ADCs compelling for contemporary bandwidth and power-constrained embedded systems (Yan et al., 20 Jan 2026, Li et al., 27 Nov 2025).

6. Design Trade-Offs and Practical Guidelines

Effective deployment of modulo ADCs involves trade-offs between analog circuit complexity, algorithmic robustness, sampling rate, and quantizer resolution:

• Comb and LPF Design: Increasing the number of comb harmonics improves the fidelity of the lowpass equivalent modulo samples but increases power and circuit complexity. High-order passive or active LPFs ensure suppression of high-frequency content (Kvich et al., 20 Jan 2025).
• Bit-Depth Versus Oversampling: Performance targets (e.g., MSE $[-\lambda, \lambda]$5) typically require $[-\lambda, \lambda]$6 bits at OF $[-\lambda, \lambda]$7; higher OF, though, can offset lower available bit-depth.
• Folding Information Encoding: One bit per sample can be robustly encoded by replacing the quantizer LSB, provided folding events (pulse width) are shorter than half the sample period (Kvich et al., 20 Jan 2025).
• Feedback Loop and Timing: Loop delay constrains the maximum achievable bandwidth; design must ensure folding and counter updates can occur reliably at target sample rates (Li et al., 27 Nov 2025, Zhu et al., 2024).
• Post-Processing Complexity: There exists a hierarchy of algorithms trading off between hardware resource usage (e.g., direct unfolding requiring strict count tracking vs. more tolerant methods like RSoD or LASSO-B²R²) and achievable reconstruction accuracy (Li et al., 27 Nov 2025, Shah et al., 2024).

7. Outlook and Integration Perspectives

Recent advances in modulo analog-to-digital conversion have made the approach broadly practical through improvements in analog front-ends, robust and efficient digital unfolding algorithms, and thoughtful integration into current digital signal processing and communications architectures. Demonstrated performance in both academia and prototype hardware points to strong potential for next-generation high-dynamic-range, bit- and power-efficient ADCs. Challenges remain in pushing practical limits on folding rate, minimizing artifact propagation in real-world noise and jitter scenarios, and extending these methods to higher-dimensional and more complex signal classes. Nonetheless, modulo ADCs are emerging as a foundational technology for unlimited dynamic-range digitization (Zhu et al., 2024, Kvich et al., 20 Jan 2025, Li et al., 27 Nov 2025, Liu et al., 2022).