AnalogMaster: End-to-End Analog IC Automation

• AnalogMaster is a full-stack framework that automates analog IC design by translating schematic images into optimized SPICE netlists, device parameters, placement, and routing.
• It integrates multimodal reasoning, Bayesian optimization, simulated annealing, and enhanced A* search to achieve end-to-end design flow with reduced error propagation.
• Experimental evaluations demonstrate significant improvements in netlist recovery and component recognition compared to traditional stage-specific automation methods.

AnalogMaster is a training-free, extensible, LLM-based framework for end-to-end automation of analog integrated-circuit design, spanning schematic image understanding, SPICE netlist generation, device sizing, placement, and routing. It was proposed in response to three stated obstacles in transferring recent LLM-driven automation practices from digital to analog design: strongly coupled performance metrics, the predominance of unstructured circuit schematic images, and the fragmentation of prior automation efforts across isolated design stages rather than full-flow optimization (Qin et al., 22 Apr 2026).

1. Scope and position within analog design automation

AnalogMaster is defined as a full-stack analog IC design pipeline rather than a stage-specific algorithm. Its input is a raw analog circuit schematic image, and its outputs include a corrected SPICE netlist, optimized device parameters, placement, and routed interconnect. The framework therefore treats analog design as a coupled perception–reasoning–optimization problem in which errors introduced early in the flow propagate into sizing and layout feasibility (Qin et al., 22 Apr 2026).

This positioning distinguishes AnalogMaster from several earlier lines of work that automate narrower subproblems. AutoAmp, for example, is an open-source command-line C++ program that takes amplifier specifications, computes component values, writes an LTSpice netlist, and supports classroom-oriented topologies such as single-stage and two-stage BJT common-emitter amplifiers, inverting and non-inverting op-amp amplifiers, an op-amp difference amplifier, and a class-A power amplifier (Patri et al., 2012). The hypernetwork-based circuit inverse-design method of “Electric Analog Circuit Design with Hypernetworks and a Differential Simulator” generates canonical two-port linear analog circuits from sampled complex voltage and current responses and then refines values with a differentiable simulator, but it is formulated around sequence generation for linear circuit synthesis rather than schematic-to-layout analog IC automation (Rotman et al., 2019). iVAMS 2.0 embeds ANN metamodels into Verilog-AMS for optimization and behavioral modeling of analog and mixed-signal blocks such as an operational amplifier and a PLL, thereby bridging behavioral and transistor-level abstraction, but it does not attempt image-to-netlist recovery or full physical design closure (Mohanty et al., 2019). AnalogGym, in turn, provides a standardized open-source evaluation suite with 30 circuit topologies in five categories, but it is benchmark infrastructure rather than a design-flow engine (Li et al., 2024).

A common misconception is that AnalogMaster is simply an LLM wrapper around existing analog CAD. The published description instead presents a hybrid workflow in which multimodal reasoning is used for schematic interpretation and parameter-space compression, while Bayesian optimization, simulated annealing, and enhanced A* search perform core downstream numerical and combinatorial tasks (Qin et al., 22 Apr 2026).

2. End-to-end pipeline and system organization

The framework is organized as a sequential but tightly coupled pipeline. The published flow is:

1. circuit image preprocessing and annotation
2. joint reasoning for image-to-netlist generation
3. parameter search agent
4. placement
5. routing (Qin et al., 22 Apr 2026)

The implementation details of each stage are concrete and heterogeneous. In preprocessing, a custom YOLOv9 detector identifies and localizes devices. EasyOCR extracts and masks text labels to prevent interference with wire tracing. Component regions are masked out to form a wire-only image, and morphological operations together with connected-component analysis recover electrical connectivity regions. The output of this stage is an annotated representation containing component bounding boxes, color-coded connectivity regions, and network identifiers (Qin et al., 22 Apr 2026).

The downstream stages retain this structural context. The netlist-recovery stage uses a multi-branch multimodal LLM configuration. The parameter-search stage uses an LLM-based agent to compress the feasible parameter space before Bayesian Optimization. Placement is performed with simulated annealing, and routing is performed with an enhanced A* search whose heuristic includes analog-specific criteria such as obstacle avoidance, electrical sensitivity, symmetry constraints, and analog design rules (Qin et al., 22 Apr 2026).

Stage	Primary method	Output
Image preprocessing and annotation	YOLOv9, EasyOCR, connectivity analysis	Annotated circuit representation
Netlist generation	Multi-branch MLLM + intent reasoning	Corrected SPICE netlist
Parameter optimization	LLM search agent + Bayesian Optimization	Sized design
Placement and routing	SA + enhanced A*	Physical design

This architecture embodies a second important clarification: AnalogMaster is not a monolithic generator. It is an orchestration framework that combines perception, symbolic reasoning, search-space reduction, black-box optimization, and analog-aware physical design under a single pipeline contract (Qin et al., 22 Apr 2026).

3. Joint reasoning for schematic image-to-netlist conversion

The most distinctive subsystem in AnalogMaster is the joint reasoning mechanism for image-to-netlist generation. The stated motivation is that direct multimodal prompting on analog schematics is error-prone because dense drawings can induce device misclassification, missed terminals, incorrect source/drain orientation in MOSFETs, and topologically invalid netlists despite syntactic plausibility (Qin et al., 22 Apr 2026).

To mitigate this, AnalogMaster constructs three heterogeneous visual inputs from the same schematic and processes them in parallel:

1. raw original circuit image
2. structurally enhanced annotated image
3. dual-view image (Qin et al., 22 Apr 2026)

Each branch receives the same chain-of-thought and multimodal in-context learning structure. The prompt asks the model to identify each component, determine each terminal’s connectivity, merge equipotential nodes, and synthesize the final netlist. The multimodal in-context learning scheme uses a representative reference schematic paired with a carefully written CoT prompt and its full intermediate reasoning, which is prepended as exemplar context to new queries (Qin et al., 22 Apr 2026).

The three branch outputs are then fused by a higher-level text LLM through intent reasoning. This fusion stage compares candidate netlists, removes inconsistent or erroneous parts, and reconstructs the most plausible circuit consistent with the inferred design intent. The paper formalizes the intuition that heterogeneous branches reduce correlated failure by expressing joint success as a union over branch candidate sets:

$$\text{Pass@1}_{\text{joint}} = \mathbb{P}\Big(y^* \in \bigcup_{b=1}^3 \mathcal{C}^{(b)}\Big) \ge 1 - \prod_{b=1}^3 \Big(1 - \mathbb{P}(y^* \in \mathcal{C}^{(b)})\Big) \ge \text{Pass@3}_{\text{single}}.$$

This suggests that the benefit is not merely extra stochastic sampling, but the use of partially uncorrelated visual encodings and a semantic reconciliation layer (Qin et al., 22 Apr 2026).

The framework also formalizes exact netlist recovery as the simultaneous correctness of both component identities and interconnections:

$$P_{\text{netlist}} = \mathbb{P}\left( \bigcap_{i=1}^N \{\hat c_i = c_i\} \cap \bigcap_{(i,j)\in\mathcal{E}} \{\hat e_{ij} = e_{ij}\} \right).$$

This definition is significant because it makes clear that AnalogMaster evaluates schematic interpretation structurally, not merely lexically (Qin et al., 22 Apr 2026).

4. Device sizing, parameter-space compression, and physical design

After topology extraction, AnalogMaster treats sizing as a high-dimensional, nonlinear, constrained optimization problem. The framework defines a figure of merit over design parameters $\mathbf{x}$ as

$$\text{FOM}(\mathbf{x}) = f\big(p_1(\mathbf{x}), \dots, p_m(\mathbf{x})\big),$$

and seeks

$$\mathbf{x}^* = \arg\max_{\mathbf{x} \in \mathcal{X}} \text{FOM}(\mathbf{x}).$$

The reported performance metrics include gain, bandwidth, power, area, and CMRR (Qin et al., 22 Apr 2026).

Rather than applying Bayesian Optimization directly to an unconstrained raw parameter space, AnalogMaster introduces a parameter search agent that reads the recovered netlist and circuit intent and compresses the feasible parameter space. This agent uses self-enhanced prompt engineering and context truncation. The stated rationale is that standard ReAct-style behavior can become overly reactive, redundant, and weak in long-horizon planning, whereas the proposed agent is encouraged to perform macro-level planning, decompose the sizing task into subgoals, and refine the search progressively (Qin et al., 22 Apr 2026).

Context truncation is a specific systems contribution. The framework retains the planning state and the latest relevant tool message while discarding obsolete intermediate feedback that will be recomputed anyway for new candidates. This is presented as preferable to generic summarization because it matches the actual workflow structure of iterative parameter search (Qin et al., 22 Apr 2026).

The reduced search space is then handled by Bayesian Optimization with Tree-structured Parzen Estimator as the surrogate, Expected Improvement as the acquisition function, 100 SPICE simulation iterations, random initialization, and median pruning for early termination of poor trials. The reported process setup is Sky130 PDK at the tt corner and $25^\circ\text{C}$ (Qin et al., 22 Apr 2026).

Placement and routing complete the flow. Placement uses simulated annealing, chosen for the combinatorial analog constraints of symmetry, common-centroid requirements, matching, and robustness to parasitics and gradients. Routing uses enhanced A* search with a heuristic incorporating obstacle avoidance, electrical sensitivity, symmetry constraints, and analog design rules. This makes AnalogMaster explicitly distinct from purely topological analog synthesis methods such as the hypernetwork-plus-differentiable-simulator approach for two-port linear circuits, where topology generation and continuous value refinement are the central tasks rather than layout realization (Rotman et al., 2019).

5. Experimental evaluation and quantitative results

The framework is evaluated using both a component-detection dataset and an end-to-end analog-circuit benchmark. For component detection, the paper constructs a Circuit Element Detection dataset from 5,681 raw images, augments it to 9,753 images, and uses an 8:1:1 train/validation/test split. The dataset covers 12 component classes: AC Source, BJT, Battery, Capacitor, DC Source, Diode, Ground, Inductor, MOSFET, Resistor, Current Source, and Voltage Source (Qin et al., 22 Apr 2026).

The end-to-end benchmark contains 15 representative analog circuits from AnalogGenies, grouped into three difficulty levels: Easy (1–4), Medium (5–10), and Difficult (11–15). Examples named in the description include an NMOS-input cascode amplifier, a CMOS differential amplifier, a differential pair with source degeneration, a multistage CMOS op amp, and a dynamic latch comparator. Four multimodal models are evaluated: GPT-4o-mini, Qwen-VL-Max, GLM-4.5V, and GPT-5 (Qin et al., 22 Apr 2026).

A task is counted as successful only if the framework correctly extracts the circuit netlist, successfully optimizes device parameters, and produces placement and routing compliant with design constraints. Under that criterion, the reported average results are:

Model	Pass@1	Pass@5
GPT-4o-mini	49.7%	72.1%
Qwen-VL-Max	53.3%	78.6%
GLM-4.5V	55.1%	74.2%
GPT-5	92.0% in the table; 92.9% in the abstract and conclusion	99.9%

The main table is described as showing GPT-5 succeeding on all 15 circuits, whereas other models degrade substantially on the most difficult cases, especially cases 13–15 (Qin et al., 22 Apr 2026).

The paper also compares AnalogMaster’s netlist-recognition module against MasaCHAI. Under Qwen-VL-Max, the average Pass@1 improves from 8.0% to 60.0% and average Pass@5 from 24.8% to 85.5%. Under GLM-4.6V, the corresponding averages improve from 8.9% to 50.2% and from 19.8% to 72.1%. At the detector level, overall component-recognition accuracy improves from 65.2% to 88.3%, with particularly large gains on capacitors, ground, and MOSFETs (Qin et al., 22 Apr 2026).

These results should be interpreted alongside the benchmark logic developed by AnalogGym. AnalogGym formalizes analog synthesis as constrained optimization under PVT variation and offers 30 topologies in five categories for fair cross-method comparison, which suggests a natural evaluation substrate for future AnalogMaster-style systems beyond the 15-circuit benchmark used here (Li et al., 2024).

6. Ablations, limitations, and technical significance

The ablation study isolates three components of the joint reasoning module: CoT, MICL, and intent reasoning. Using Qwen-VL-Max, the full framework achieves average Pass@1 of 53.3% and Pass@5 of 78.6%. Removing CoT reduces these to 39.6% and 64.0%; removing MICL reduces them to 32.0% and 55.3%; removing intent reasoning reduces them to 29.3% and 54.9% (Qin et al., 22 Apr 2026).

The interpretation given in the paper is differentiated rather than generic. CoT matters most for complex connectivity reasoning. MICL is especially helpful when wiring is visually messy or ambiguous. Intent reasoning is described as the most critical robustness mechanism because it corrects branch-level errors and mitigates single-point failure. The difficult cases 13–15 remain solvable only under the full framework, which the authors use as evidence that the modules are complementary rather than redundant (Qin et al., 22 Apr 2026).

Several limitations are explicitly acknowledged. Performance depends materially on the capability of the underlying MLLM; GPT-5 is markedly stronger than the other evaluated models. Finite context windows constrain how many branches and how much tool history can be used, motivating context compression and truncation. Additional branches could improve coverage but would increase input length, computational cost, and redundancy. Even after LLM-based parameter-space compression, Bayesian Optimization can still fail to reach targets within limited iterations on hard cases. The evaluation scope is 15 circuits, and no claim of universal coverage is made. Because the framework is designed for full automation, upstream extraction errors can still propagate downstream (Qin et al., 22 Apr 2026).

The broader significance of AnalogMaster lies in its attempt to unify stages that previous systems typically separated. AutoAmp automates educational amplifier synthesis and LTSpice export (Patri et al., 2012); iVAMS 2.0 accelerates optimization and behavioral simulation through ANN metamodels in Verilog-AMS (Mohanty et al., 2019); hypernetwork-based inverse design addresses topology generation and value refinement for canonical two-port linear circuits (Rotman et al., 2019); AnalogGym standardizes evaluation (Li et al., 2024). AnalogMaster’s contribution is to connect visual schematic understanding, topology extraction, sizing optimization, placement, and routing within one workflow. A plausible implication is that its primary novelty is not any single algorithmic primitive, but the explicit coupling of multimodal reasoning with classical analog optimization and layout synthesis under an end-to-end success criterion (Qin et al., 22 Apr 2026).