EEschematic: AI Analog Schematic Generation

• EEschematic is a multimodal AI agent that converts textual SPICE netlists into human-editable analog schematics using iterative chain-of-thought reasoning.
• It employs a Visual Chain-of-Thought strategy to iteratively refine device placement and wiring, ensuring symmetry and design clarity.
• The system integrates text, images, JSON schemas, and reasoning to streamline analog circuit design and reduce manual conversion errors.

EEschematic is an advanced AI agent leveraging Multimodal LLMs (MLLMs) for automatic schematic generation of analog circuits from textual SPICE netlists. It addresses the limitations of previous LLM-based approaches, which primarily output textual formats lacking visual interpretability, by directly producing human-editable schematic diagrams that align with professional design standards for clarity, symmetry, and correctness.

1. Concept and Objective

EEschematic is designed to translate SPICE netlists into visual schematic diagrams that serve as the backbone of analog circuit understanding and verification. The framework unifies four core modalities: (1) textual circuit descriptions, (2) visual representations of the schematic, (3) symbolic encodings of placement and wiring via JSON, and (4) iterative chain-of-thought reasoning based on reference examples. This integrated approach eliminates the manual conversion step that frequently introduces design errors and impedes rapid prototyping in mixed human/ML design environments.

Traditional netlist generators and LLM-based systems—such as Schemato (Matsuo et al., 21 Nov 2024)—have demonstrated utility mainly on netlist-to-code translation but lack robust support for complex, visually interpretable schematics. EEschematic advances this by tightly coupling reasoning and generation across visual and symbolic domains.

2. Methodological Framework

Multimodal Reasoning Architecture

EEschematic is built around multimodal LLMs, exemplified by Gemini 2.0 Flash, which jointly process text, images, and structured data. For schematic creation, the agent ingests:

• The SPICE netlist specifying device connectivity and model parameters.
• Natural language prompts describing circuit function and expected topology.
• Reference schematic images and JSON schemas encoding device placement and wiring geometry.

The agent formulates the schematic generation task as an inner optimization loop, iteratively improving both placement and wiring configurations using a Visual Chain-of-Thought (VCoT) strategy.

Visual Chain-of-Thought Strategy

The VCoT process operates as follows:

1. Initial Placement: The MLLM utilizes in-context few-shot analog substructure examples—JSON schemas plus natural language orientation descriptions—to lay out devices with respect to symmetry and spatial organization.
2. Custom Wiring Algorithm: Based on node and terminal information, an initial wiring scheme is rendered.
3. Iterative Refinement: The MLLM receives the current schematic (rendered image + JSON) and compares it to curated reference examples, identifying misalignments, wire tangling, or connectivity errors. It then outputs structured reasoning (“This transistor should be mirrored for symmetry,” “Wire routing should be compacted”) driving further iterations.
4. Convergence: The loop repeats until predefined correctness and aesthetics criteria are met.

The process enforces a feedback-driven refinement, markedly improving schematic clarity compared to static one-shot generation approaches.

3. Multimodal Integration and Few-shot Placement

The multimodal fusion hinges on a shared context built from four representations:

• SPICE netlist (original textual circuit topology),
• Natural language descriptions (functional and orientation cues),
• Schematic diagrams (visual output and feedback),
• JSON schemas (precise geometric/wiring specification).

Few-shot learning is enabled using six key analog substructure examples. These comprise device blocks (e.g., single transistor, current mirror, cascode pair) with both their JSON placement and textual orientation descriptions. For instance, “Single transistor. The source and drain are connected…” or “Two transistors with gates connected together…” guide initial layout.

Table: Sub-circuit Placement Examples

Example #	JSON schema devices	Orientation description
1	Q1	“Single transistor. The source and drain are connected…”
2	Q2, Q3	“Two transistors with gates connected together…”
…	…	…

This approach enhances spatial regularity and symmetry, critical for schematic legibility.

4. Experimental Evaluation and Performance

The agent is evaluated on three representative circuits: CMOS inverter, five-transistor operational transconductance amplifier (5T-OTA), and telescopic cascode amplifier. Metrics include:

• Visual Correctness: Valid connectivity, proper device placement, and node mapping (scored 9/10 for all circuits).
• Aesthetics: Manual scoring for symmetry, compactness, and visual coherence (inverter and 5T-OTA: 9/10; telescopic cascode: 5/10, reflecting complexity).
• Iteration Counts: Placement and wiring converge within 3–4 iterations for simpler circuits, and up to 6 for more complex ones.

Figures demonstrate the schematic evolution from initial (often cluttered or asymmetric) layouts to final, visually optimized results, confirming effective VCoT-guided refinement.

5. Technical Process Details

System integration links schematic renderer outputs (images + JSON) to the MLLM for both evaluation and feedback. The optimization process can be concisely conceptualized in LaTeX as:

$$S^{(i+1)} = \mathcal{F} \Big( S^{(i)}, \text{Reference Examples}, \text{VCoT Reasoning} \Big)$$

where $S$ is the schematic state and $\mathcal{F}$ is the iteration function induced by chain-of-thought inference and reference matching.

Placement iterations leverage the library of substructures; wiring iterations refine interconnections for node compactness and graphical clarity.

6. Applications, Limitations, and Future Directions

EEschematic’s multimodal generation capability positions it for integration into contemporary analog circuit design workflows:

• Design Automation: Reduces manual drafting time and associated error risk for initial schematic generation.
• Educational Utility: Enables interactive learning, guiding novices through schematic connectivity and layout principles.
• Verification Support: Streamlines functional validation by rendering machine-generated netlists into human-readable diagrams.

Current limitations include the focus on fundamental analog blocks (scalability to larger, hierarchical designs untested), subjective aesthetic evaluation metrics, and occasional structural errors post-optimization. Future work may address these via objective visual quality benchmarks, constraint-driven refinement, and extension to complex multi-stage circuits.

7. Summary and Significance

EEschematic synthesizes advances in multimodal AI, schematic rendering, and analog design into a functional system for direct netlist-to-schematic translation. Its fusion of in-context learning by example, Visual Chain-of-Thought reasoning, and iterative optimization achieves high correctness and visual quality for canonical analog circuits. It extends previous LLM-based netlist translation efforts by robustly supporting visually interpretable output, mitigating previous failure modes on complex circuits. The approach lays the groundwork for scalable, automated schematic tools and sets a standard for AI-driven design readability in professional and educational domains (Liu et al., 19 Oct 2025).