AMSnet-KG: Automated AMS IC Design

• AMSnet-KG is a curated dataset and knowledge graph that integrates schematic data, SPICE netlists, and multi-level annotations for AMS circuits.
• It employs a graph schema with Neo4j to enable precise circuit fragment retrieval and LLM-driven strategy extraction for automated netlist assembly.
• The framework uses Bayesian optimization in a closed-loop design flow to refine transistor sizing and ensure performance targets are met.

AMSnet-KG is a curated dataset and knowledge graph designed to advance the automation of analog and mixed-signal (AMS) integrated circuit (IC) design using LLMs in conjunction with retrieval-augmented generation (RAG) methods. It encapsulates schematic data, SPICE netlists, comprehensive local and global annotations, and a graph-based schema for storing and querying knowledge relevant to AMS circuits. AMSnet-KG enables a closed-loop, minimal-human-intervention design flow for AMS circuits, integrating knowledge retrieval, LLM-based synthesis, automated topology assembly, Bayesian optimization of device parameters, and iterative design refinement driven by simulation feedback (Shi et al., 2024).

1. Dataset Composition and Annotation Framework

AMSnet-KG comprises 894 manually extracted AMS circuit schematics from a range of published textbooks and research papers. The dataset covers circuit types including operational amplifiers (single-stage, two-stage, telescopic, folded-cascode), comparators (strong-arm latch, double-tail), bandgap references, low-dropout regulators (LDOs), ADC building blocks, bias generators, and RC filters. For each circuit, AMSnet-KG supplies a SPICE-formatted netlist (.sp file), which adheres to a consistent device pin ordering (drain, gate, source, bulk for MOSFETs) and employs an algorithmic approach to net naming and connectivity via detected pixel adjacency, junction node insertion, and orientation-based pin ordering.

Each circuit entry is augmented with two levels of annotation:

• Local annotations: Define pin functions (e.g., "Vin+ → net8"), label building blocks (“differential pair = {M1, M2}”, “current mirror = {M5…M8}”), encode device symmetry constraints ("share_parameters" rules), and specify binding between schematic nets and testbench ports.
• Global annotations: Capture architectural descriptors (e.g., "gain: high", "load: current mirror"), performance specialties (e.g., "high DM gain", "low output swing"), and succinct circuit summary phrases (“5-transistor opamp”, “2-stage amplifier + Miller cap”).

Performance testbenches are provided for dominant AMS metrics including differential mode gain, CMRR, PSRR, gain-bandwidth product (GBW), phase margin, offset, delay, and power.

2. Knowledge Graph Schema and Query Mechanism

AMSnet-KG models domain knowledge as a knowledge graph with explicit entity and relation types:

• Entities: Circuit nodes associated with schematic images, netlists, and all annotations; string nodes encoding annotation values or testbench names.
• Relations: Edge-labels indicating functional roles, architectural traits, or performance attributes, representing triplets of the form <subject, relation, object>.

The knowledge graph is implemented using Neo4j, with retrieval conducted by Cypher queries or direct triplet indexing. No dense vector embedding is performed; instead, the graph structure and explicit triplets are leveraged for precise, constraint-aware retrieval, enabling granular subgraph extraction for downstream prompt assembly.

3. Retrieval-Augmented Generation (KG-RAG) Design Flow

The LLM-driven circuit design process operates as a chained pipeline leveraging the annotated knowledge graph:

1. Design Strategy Extraction: LLMs are prompted—using chain-of-thought (CoT) reasoning and in-context learning (ICL)—to generate a textual "circuit structure" strategy based on given specifications (e.g., target topology, required architecture, and process node constraints). Few-shot exemplars encode standard generation patterns.
2. Triplet Generation: The LLM outputs a canonicalized sequence of relation triplets describing the intended circuit organization.
3. Subgraph Retrieval: Each triplet is used to query AMSnet-KG, retrieving corresponding circuit fragments (schematics, netlists, and associated testbenches).
4. Prompt Fusion and Netlist Assembly: Retrieved netlists are programmatically fused, wiring fragments according to pin and net annotations, producing a unified SPICE netlist ready for parameterization and simulation. Testbenches are similarly bound through matching net nomenclature.

This structured approach avoids knowledge loss or misalignment during retrieval and ensures that circuit assembly is exactly specification-driven.

4. Parameter Optimization and Closed-Loop Regeneration

Transistor sizing is formulated as a constrained black-box optimization problem. The objective is to maximize a custom figure-of-merit (FoM):

$$FoM(x) = \sum_i w_i \cdot \frac{\min(f_i(x), J_i) - f_{\min}}{f_{\max} - f_{\min}}$$

where $x$ is the vector of device geometries and passive values, $f_i(x)$ are simulated performance metrics (e.g., gain, CMRR), $J_i$ are target thresholds, and $w_i$ are weights.

The flow adopts Gaussian Process (GP) surrogate modeling:

• Zero-mean prior $m(x)=0$ and kernel $k(x, x')$
• Posterior mean and variance as:

$\mu(x_*) = k(x_*, X)^\top K^{-1} y$

$$\sigma^2(x_*) = k(x_*, x_*) - k(x_*, X)^\top K^{-1} k(x_*, X)$$

Expected improvement (EI) guides acquisition:

$a(x) = \mathbb{E}[\max(0, f(x) - f(x^+))]$

Bayesian Optimization (BO) operates as follows (Algorithm 1):

1. Sample initial points from a constraint-augmented parameter space (reduced DOF via symmetry constraints).
2. Fit the GP surrogate.
3. For each iteration, select the parameter set maximizing EI, simulate performance, and update GP.
4. Return the best parameter vector upon termination.

If the best topology after sizing fails to meet all target specifications or is inefficient in area/power, a simulation-feedback loop is activated: actual performance metrics and the previous design are included as few-shot input for the LLM, which is prompted to generate an alternative topology. The process iterates retrieval, assembly, and optimization until requirements are satisfied or all annotated topologies are exhausted.

5. Case Study: Operational Amplifier and Comparator Auto-Design

Two detailed case studies are presented to illustrate end-to-end flow.

Operational Amplifier:

• Target specs: Gain > 80 dB, CMRR > 80 dB, PSRR > 80 dB, GBW > 10 MHz, phase margin > 60°, load capacitance = 100 pF.
• Initial strategy: LLM proposes a two-stage op-amp (differential NMOS pair + PMOS current-mirror load, then common-source amplifier stage with PMOS load, Miller compensation).
• Assembly: Retrieval and netlist fusion yields complete .sp circuit with all required sub-blocks.
• Sizing: 19 raw device parameters (reduced to 15 DOF via constraints). BO converges more rapidly and to higher FoM when symmetry annotations are used; unconstrained sizing is slower with lower final FoM. The best first-attempt gain is ≈66 dB, triggering topology regeneration.
• Topology regeneration: LLM proposes telescopic-cascode input stage; subsequent sizing achieves Gain ≈80.85 dB, CMRR ≈99 dB, PSRR ≈91 dB, GBW ≈14.3 MHz, phase margin ≈60.5°, meeting all specs.

Strong-Arm Latch Comparator:

• Target specs: Sample frequency 1 GHz, offset <100 µV, propagation delay ≤1 ns, power <100 µW.
• Strategy: LLM identifies two candidate topologies (strong-arm latch, double-tail latch), selects the strong-arm variant.
• Sizing: 22 raw parameters (reduced to 10 DOF). Final results: offset ≈35 µV, propagation delay ≈12 ps, power ≈88 µW.

6. Openness, Future Extensions, and Current Limitations

AMSnet and AMSnet-KG will be public upon publication. Potential extensions include:

• Expansion to additional AMS circuit classes (e.g., low-noise amplifiers, mixers, ADC front-ends), and broader process node coverage.
• Storage of direct parameter-performance mappings for enabling few-shot sizing without full Bayesian optimization.
• Training of AMS-specialized foundation models using KG-aware pretraining.
• Integration of ML-based performance predictors to reduce SPICE simulation dependency.

This suggests increased automation scope and design space coverage, though the flow's efficacy is currently bounded by LLM reliability in triplet extraction and strategy generation, the speed and capacity of SPICE for simulation (≈2,000 evaluations per design), and the manual process required for validation of net connectivity and annotation accuracy (~96–97% achieved). A plausible implication is that scaling AMSnet-KG's coverage and automating niche topology integration would mitigate bottlenecks in emerging AMS IC domains (Shi et al., 2024).