AnaFlow: Agentic Framework for Analog Sizing

• AnaFlow is an agentic LLM-driven framework for analog circuit sizing that combines specialized agents and algorithmic optimization to deliver transparent design decisions.
• It divides the sizing process into four phases where agents parse SPICE netlists, assess circuit performance, and refine parameters with interpretability at every step.
• It significantly reduces full simulation calls by over 20–30× compared to conventional reinforcement learning approaches, ensuring sample efficiency and auditability.

AnaFlow is an agentic LLM-driven framework for analog circuit sizing, designed to address the twin challenges of sample-inefficiency and lack of explainability endemic to prior automated analog electronic design automation (EDA) approaches. It orchestrates a multi-agent workflow in which specialized LLM-based agents parse SPICE netlists, reason about circuit topology, and iteratively refine sizing parameters using a combination of human-style reasoning and algorithmic optimization. AnaFlow enables the synthesis of analog designs with transparent justifications for each parameter update, while reducing the total number of required circuit simulations by over an order of magnitude compared to conventional reinforcement learning (RL) or black-box optimization flows (Ahmadzadeh et al., 5 Nov 2025).

1. Motivation and Problem Context

Analog/mixed-signal circuit design, in contrast to digital design automation, is typified by highly non-convex dependencies between performance metrics (such as gain, phase margin, bandwidth, noise, and power consumption) and physical/electrical design variables (transistor dimensions, bias currents, passives). Historically, sizing such circuits has relied on iterative manual tuning based on expert heuristics. Automated approaches—including genetic algorithms (GA), Bayesian optimization (BO), and RL—have led to notable runtime and energy efficiencies but require 10⁴–10⁵ simulations for GA, and hundreds to thousands for advanced RL (Ahmadzadeh et al., 5 Nov 2025).

A major limitation of prior art is the absence of interpretability: automated solutions output a sizing vector (e.g., transistor width/length assignments) without articulating rationale or trade-off analyses, thereby hindering verification and adoption. AnaFlow is specifically motivated by the need to (1) minimize expensive simulator calls and (2) provide per-step, human-readable reasoning for its decisions.

2. System Architecture

AnaFlow divides the circuit sizing problem into four architectural phases, with two collaborating LLM agents per phase. All agents are context-prompted, with access to the netlist, historical variable sets, simulation traces, and reasoning logs. The system operates as a workflow controller—invoking external simulation tools (e.g., SPICE for .op, .ac, .tran) and optimizers (BO, RL)—while maintaining a complete record of agent rationales.

The high-level execution structure is illustrated below (ASCII "flow sketch" verbatim from (Ahmadzadeh et al., 5 Nov 2025)):

+------------------------------------------------------------+ | | | Phase 1 --► Circuit Explainer ─► Matching Finder | | │ │ | | ▼ ▼ | | DC Goal Setter ─► Initial Designer | | | +------------------------------------------------------------+ │ ▼ +--------------------------------------+ | Phase 2: DC-OP Loop | | [Iterate ~5–10×] | | DC Reviewer ──► DC Sizer ──► (back)| +--------------------------------------+ │ ▼ +--------------------------------------+ | Phase 3: Reasoning-Only Loop | | [Up to 20 full SPICE sims] | | Specs Reviewer ──► Reasoning Sizer | +--------------------------------------+ │ ▼ +--------------------------------------+ | Phase 4: Optimizer-Equipped Loop | | [until specs met] | | Advisor Reviewer ──► Equipped Sizer| +--------------------------------------+

Each agent fulfills a specialized task: topology parsing, device matching, DC operating point assessment, parameter proposal, or optimizer invocation. The agents write detailed "reasoning" paragraphs after each action, which form a complete human-readable trace.

3. Detailed Workflow and Agent Reasoning

Phase 1: Initial Analysis

• Circuit Explainer: Parses SPICE netlist and annotates the role of each device (e.g., differential pair, cascode load).
• Matching Finder: Enforces layout-aware device matching constraints (e.g., W₁=W₂ for current mirrors).
• DC Goal Setter: Determines target DC values for node voltages and device currents.
• Initial Designer: Generates initial guesses for sizing variables based on manual best practices (e.g., L ≈ 3×L_min for improved gain).

Phase 2: DC-Operating-Point (DC-OP) Refinement

• Alternates between DC Reviewer, which analyzes .op simulations and diagnoses device modes (e.g., V_DS<V_sat→triode), and DC Sizer, which adjusts device dimensions to align with target regimes.

Phase 3: Reasoning-Only Performance Loop

• Specs Reviewer evaluates simulated performance (gain, phase margin, bandwidth, power), identifies metric shortfalls (Δ_k = M_k^req – M_k(x)), and records nuanced feedback regarding trade-offs.
• Reasoning Sizer proposes parameter updates, leveraging the memory of previous simulation outcomes to avoid local minima and fruitless search regions.

Phase 4: Optimizer-Equipped Loop

• If the improvement over a sliding window of iterations falls below a threshold (e.g., ΔFOM/FOM < ε), the Advisor Reviewer instructs Equipped Sizer to invoke a black-box optimizer (BO or RL). The selection of the optimizer is grounded in the empirical evidence of stagnation:

$$\forall\,i\in\{t-L+1,\dots,t\}:\quad \Delta FOM(i)/FOM(i-1) < \epsilon$$

• Upon optimizer completion, the recommended parameters are integrated and explained in the log.

At every transition, a detailed, standardized explanation is appended by each agent, producing a transparent and auditable design trace.

4. Adaptive Simulation Regimes and Sample Efficiency

AnaFlow's key efficiency innovation is its adaptivity in simulation selection, dynamically choosing among DC .op, full AC/transient, or optimizer invocations based on real-time analysis of progress. Simulation decisions are governed by detecting stagnation or large DC violations—only running costly full simulations when necessary. The following notations are used to measure sample efficiency:

• $N_{\text{full}}:$ Total full (AC+tran) simulations
• $N_{\text{DC}}:$ Total DC .op simulations
• $\text{TotalSim} = N_{\text{full}} + N_{\text{DC}}$
• $$\text{Convergence rate} = \text{FOM}_{\text{final}}/N_{\text{full}}$$

Empirical evidence shows that AnaFlow reduces full simulation calls by a factor of 20–30× compared to RL-based approaches for comparable circuit topologies.

5. Mathematical Formulation and Algorithmic Details

The analog sizing task is formally defined as a nonlinear constrained optimization:

$$\min_{x\in\mathcal{X}} f(x) = \sum_{k=1}^K w_k \left[ M_k^{\text{req}} - M_k(x) \right]_+^2$$

subject to device-level DC constraints: $$g_i(x) = V_{DS,i}^{\text{req}} - V_{DS,i}(x) \leq 0$$ where $x$ is the design-variable vector (e.g., $[W_1, L_1, \ldots, I_{\text{bias},m}]$), $M_k$ are circuit metrics, and $\mathcal{X}$ represents box constraints. Bayesian Optimization when invoked models $f(x)$ as

$f(x) \sim \mathcal{GP}(\mu(x), k(x,x'))$

and selects candidates via Expected Improvement:

$$\alpha_{\text{EI}}(x) = \mathbb{E}[\max(0,\,f(x)-f^+)]$$

When the RL policy is active, the reward is

$$r_t = -\sum_k w_k [M_k^{\text{req}} - M_k(x_t)]_+^2$$

and the actor–critic is updated accordingly.

6. Case Studies and Empirical Results

AnaFlow has been demonstrated on two canonical test cases:

Circuit Topology	Params	AnaFlow Full Sims	RL Baseline Full Sims	AnaFlow Total Sims	Convergence Time
Two-Stage Miller Op-Amp	12	9	1035	15	24 min
Folded–Cascode Op-Amp + CMFB	28	14 (+50 opt.)	1808	64	29 min

RL Baseline refers to the AnaCraft RL system.

Although AnaFlow incurs higher per-agent-cell latency, its pipeline results in a substantial reduction in full AC/transient simulations and thus overall tool compute costs for mid/large-scale designs. In both test cases, AnaFlow fully meets all user specifications, and every design step remains interpretable through the reasoning logs.

7. Explainability and Trace Auditability

A defining feature of AnaFlow is its ability to generate per-iteration natural language explanations for every parameter change, simulation invocation, and optimization decision. Each agent annotates steps such as:

• Diagnosis: "M5’s V_DS=0.55 V falls below the saturation target of 0.6 V → transistor in triode region → reduces output resistance and gain."
• Proposed Fix: "Increase L5 to 240 nm to restore saturation; compensate by increasing W5 by 10%."

All explanations are formatted and stored in an accessible archival log for future review, audit, or critique. This feature enables unprecedented transparency in analog design flows, distinguishing AnaFlow from all prior black-box optimization-based tools.

8. Outlook and Potential Extensions

The paradigm introduced by AnaFlow opens avenues for further research in analog EDA. Potential areas of extension include:

• Upstream integration with automatic topology generation.
• Multi-fidelity and behavioral-level simulation to further reduce the reliance on full SPICE calls.
• Agents for process-voltage-temperature (PVT)-robust design.
• Deep integration of layout-awareness, allowing agent reasoning to encompass parasitic and yield considerations.

AnaFlow demonstrates that orchestrating collaborative LLM agents—each mimicking analog designer heuristics—can produce both sample-efficient and fully explainable analog sizing flows, signifying a marked shift in EDA methodologies for analog and mixed-signal circuits (Ahmadzadeh et al., 5 Nov 2025).