AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout

Abstract: Design automation has the potential to substantially improve the efficiency of analog integrated circuit (IC) design. However, existing algorithms and tools typically focus on individual stages, such as device sizing, placement, or routing, and still require significant manual intervention to complete the full design flow. While LLMs have recently demonstrated remarkable success in automating digital IC design workflows, these advances cannot be directly transferred to analog IC design. Key challenges include strongly coupled performance metrics, the predominance of unstructured circuit schematic images, and the fact that most prior approaches address only isolated stages of the analog design process, limiting their ability to capture end-to-end performance impact. To address these challenges, we propose AnalogMaster, an extensible, LLM-based framework that enables end-to-end automation of analog IC design through a unified pipeline spanning circuit image-to-netlist generation, parameter optimization, placement, and routing. AnalogMaster integrates a joint reasoning mechanism that leverages in-context learning and intent reasoning to achieve accurate and robust image-to-netlist conversion. A parameter search agent integrating self-enhanced prompt engineering and context truncation is developed for effective device sizing and downstream physical design. Experimental evaluations on 15 representative circuits with varying levels of complexity demonstrate strong and consistent performance across multiple models. In particular, GPT-5 achieves success rates of 92.9% and 99.9% on Pass@1 and Pass@5, respectively. These results validate the effectiveness and robustness of the proposed framework and establish a practical paradigm for applying LLMs to full-stack analog IC design automation.

• The paper presents an LLM-based framework that automates the entire analog IC design process from circuit image analysis to final layout, achieving up to 92.9% Pass@1 performance.
• It employs joint reasoning with chain-of-thought and multimodal in-context learning to enhance netlist extraction and resolve topological ambiguities.
• It integrates agent-based parameter search with Bayesian Optimization, Simulated Annealing, and A* search to optimize device sizing, placement, and routing, outperforming prior benchmarks.

AnalogMaster: An LLM-Based Framework for End-to-End Automated Analog IC Design

Introduction

Analog integrated circuit (IC) design automation has long lagged behind digital IC automation due to strong stage dependencies, the lack of structured datasets, and the complexity of analog performance metrics. The "AnalogMaster" framework (2604.20916) addresses these challenges by tightly integrating LLMs, multimodal LLMs (MLLMs), agent-based parameter search, and classical optimization techniques into a unified, fully automated analog IC design flow—from circuit image analysis and netlist extraction through device sizing, placement, and routing.

Figure 1: Workflows of AnalogMaster: The circuit image, preprocessed via YOLO-based detection and connectivity analysis, is converted into a netlist using the proposed joint reasoning mechanism. A parameter search agent compresses the device parameter space, followed by BO for sizing, SA for placement, and A

for routing—enabling a fully automated design flow.*

Circuit Image Annotation and Preprocessing

The framework begins by addressing the inherent difficulties of interpreting analog circuit images. A large, high-quality dataset of annotated circuit schematics was constructed, enabling training of a YOLOv9 detector for robust component identification. Textual labels are recognized and masked separately via OCR (EasyOCR), and morphological processing isolates wire-only regions for accurate connectivity inference. Each connection node is distinctly annotated, resolving both topological and semantic ambiguities in the raw image.

Figure 2: The process flow for circuit image analysis: input image, component detection, text OCR, wire-only extraction, node/connection extraction, and annotated output.

Joint Reasoning for Netlist Extraction

Chain-of-Thought and Multimodal In-Context Learning

AnalogMaster introduces a joint reasoning pipeline, leveraging CoT prompting and multimodal in-context learning (MICL) to maximize the netlist extraction fidelity from annotated circuit images. This method decomposes netlist extraction into stepwise tasks—component identification, terminal connectivity inference, and node merging (Figure 3)—using structured prompts and paired exemplar images as context.

Figure 4: Overview of the Joint Reasoning workflow combining parallel MLLM branches and result synthesis for high-fidelity netlist extraction.

Figure 3: A Chain-of-Thought prompt example guiding MLLM netlist extraction through sequential component and connection analysis.

Figure 5: Multimodal context learning, using reference images and step-by-step prompts to create a robust recognition logic for netlist extraction.

Parallel and Intent Reasoning

Three heterogeneous visual representations—raw, connectivity-annotated, and dual-view—are processed in parallel, independently producing netlist hypotheses. These outputs are then synthesized by a high-level LLM that employs "intent reasoning," aligning structurally correct segments and correcting inconsistencies or spurious components through cross-view consensus.

Figure 6: Intent reasoning synthesizes partial, potentially-inconsistent netlists into a single, fully-correct result.

Context Compression

AnalogMaster compresses reasoning traces into distilled contextual representations via LLM-based semantic extraction. This limits attention overhead without sacrificing essential circuit information—a key consideration for maintaining scalability and efficiency in long-context LLM workflows.

Figure 7: Context compression via LLM, discarding irrelevant records and preserving only task-relevant reasoning for downstream optimization.

Parameter Search Agent and Optimization

AnalogMaster's agent-based parameter optimization addresses the notorious challenge in analog design: co-optimizing device sizing amid high-dimensional, coupled, and nonconvex parameter spaces. The agent uses self-enhanced prompt engineering and a "Thought–Action–Observation" loop (rather than classical ReAct agent modes) to compress the design space based on circuit topology, functional constraints, and prior analysis outputs. Importantly, obsolete or irrelevant historical tool messages are pruned to avoid context bloat and degradation of reasoning.

Figure 8: Context truncation eliminates non-essential tool messages while preserving planning-critical information.

After parameter space reduction, Bayesian Optimization (BO, TPE+EI) is employed for device sizing, while Simulated Annealing (SA) and advanced A* search perform placement and analog-specific routing, respectively.

Dataset Construction and Benchmarking

A comprehensive Circuit Element Detection (CED) dataset of 9,753 images was curated, outperforming existing alternatives (e.g., v3qwe from MasaCHAI) for detection accuracy and class coverage.

Figure 9: Comparison of circuit element detection accuracy and wire continuity between MasaCHAI's and AnalogMaster's datasets.

Evaluation was performed on 15 circuits of varying complexity drawn from the AnalogGenies benchmark with performance measured by Pass@k (the probability of a correct output within $k$ attempts) per component task and at the full-flow level. Four models were compared as MLLM backends, including Qwen-VL-Max, GLM-4.5V, GPT-4o-mini, and GPT-5.

Numerical Results and Ablation

AnalogMaster demonstrated state-of-the-art performance: GPT-5 achieved Pass@1 of 92.9% and Pass@5 of 99.9% for end-to-end analog IC design tasks, setting a new benchmark for MLLM-based analog automation. The full analog IC design pipeline—including netlist recognition, device sizing, placement, and routing—was reliable across all benchmark circuits with the most capable generative backend.

Ablation studies confirmed the significance of each architectural element: joint reasoning, CoT, MICL, and intent reasoning all contributed substantially to robustness and accuracy, especially for complex analog topologies. Removal of intent reasoning, in particular, led to drastic failures due to the propagation of error-induced inconsistencies downstream.

A head-to-head comparison with MasaCHAI showed that AnalogMaster's netlist extraction is substantially more accurate, ascribed mainly to higher-quality circuit image annotation, advanced prompt engineering, and multi-view joint reasoning.

Figure 10: A complete example of AnalogMaster's flow from image, through annotation, netlisting, parameterization, placement, and final routed layout.

Implications and Future Directions

AnalogMaster establishes a new paradigm, showing LLMs (when properly scaffolded with multimodal I/O, advanced agents, and classical optimization) can deliver fully automated, image-to-layout analog IC design at a practical scale and reliability. Its architecture is extensible to more challenging scenarios (mixed-signal designs, enhanced multimodal reasoning), provided that base MLLM capabilities continue to improve and relevant domain-specific datasets are expanded.

Several implications emerge:

• Design productivity: Eliminates labor-intensive manual netlisting, parameter estimation, and layout hand-offs, potentially enabling broader adoption of analog EDA automation in industry.
• MLLM benchmarking: Offers an end-to-end, circuit-centric benchmark for evaluating multimodal model efficacy on hard, practically relevant tasks.
• Robustness: The multi-branch, multi-modal consensus strategies address common failure modes (hallucinations, aliasing, structural misinterpretation) prevalent in earlier LLM-based analog workflows.
• Generalizability: The approach can, in principle, extend seamlessly to other engineering workflows requiring multimodal perception, sequential reasoning, and high-dimensional planning.

Future advances may focus on augmenting MICL with domain-adaptive pretraining, interactive agent frameworks for multi-objective design trade-offs, and scalable handling of even larger, more diverse analog/mixed-signal libraries and process rules.

Conclusion

AnalogMaster (2604.20916) demonstrates that with structured reasoning, agent-based parameter optimization, and rigorous multimodal context integration, LLM-powered frameworks can automate the entire analog IC design process, from circuit image to final layout. Its results set a new reference point for LLMs in analog EDA, both theoretically and practically, with broad potential impact on design productivity and AI integration in physical design methodologies.