Netlist Construction Techniques

• Netlist construction is the process of converting high-level circuit specifications into explicit connectivity representations suitable for simulation, verification, and fabrication.
• It employs advanced techniques such as deep-learning-based image processing, graph neural networks, and hierarchical programmatic models to extract components and connectivity.
• The methodologies ensure accurate net naming, pin ordering, and parameter extraction across analog, digital, and quantum circuits, optimizing automated design workflows.

Netlist construction is the process of translating a high-level circuit specification—such as a schematic diagram, mathematical description, programmatic model, or spatial discretization—into an explicit textual or data-structured representation of circuit connectivity and device parameters, suitable for automated simulation, verification, or fabrication. The netlist serves as an essential intermediate artifact in the design, analysis, and generation of analog, mixed-signal, digital, electromagnetic, and quantum circuits. This article assembles a rigorous account of state-of-the-art netlist construction methodologies across a spectrum of modern applications, with a particular focus on AI-driven, differentiable, and hierarchical workflows.

1. Input Modalities and Preprocessing Techniques

Netlist construction pipelines are initiated from diverse input formats, each requiring distinct preprocessing and abstraction strategies:

• Schematic Images (Raster/Vector): Automated pipelines such as AMSNet, SINA, and Masala-CHAI operate directly on scanned textbook pages or high-resolution PDFs. These systems leverage binarization and object detection (e.g., YOLO-v8, YOLOv11) to extract component bounding boxes, instantiate instance-level labels (e.g., “NMOS,” “PMOS,” “C,” “junction”), and parameterize orientation angles (Tao et al., 2024, Aldowaish et al., 29 Jan 2026, Bhandari et al., 2024).
• Circuit Graphs and Partial Netlists: AI-driven frameworks such as GNN-ACLP and GraCo accept incomplete netlists or port-level circuit hypergraphs. These models reconstruct full connectivity by predicting missing links or synthesizing new subgraph elements, using message-passing graph neural networks and reinforcement learning (Pan et al., 14 Apr 2025, Uhlich et al., 2024).
• Mathematical or Computational Descriptions: In electromagnetic and thermal domains, netlists are algorithmically generated from structured grid discretizations using techniques like the Finite Integration Technique (FIT), mapping nodes, edges, and material matrices onto explicit circuit branches (Casper et al., 2018).
• Hierarchical or Programmatic Models: Python frameworks and computational graph-based JSON schemas describe the circuit’s modular structure explicitly, enabling hierarchical flattening, parameter passing, and symbolic expressions for device characteristics (Long et al., 2024, Gutiérrez et al., 2023).
• Quantum Circuits: Quantum Netlist Compiler (QNC) ingests unitary matrices or state vectors and decomposes them into primitive gate operations suitable for OpenQASM representation (Aktar et al., 2022).

2. Component and Connectivity Extraction

Central to netlist construction from schematic or image-based sources is the accurate identification of components and electrical connectivity:

• Object Detection: Deep convolutional detectors (YOLOv8, YOLOv11) are trained on manually curated schematic corpora to localize and classify all electronic symbols (transistors, passives, sources, etc.), delivering box coordinates, class assignments, and, where applicable, inductive or algorithmic orientation (e.g., arrow for MOSFET type) (Tao et al., 2024, Bhandari et al., 2024, Aldowaish et al., 29 Jan 2026).
• Connected-Component Labeling / Wire Extraction: Morphological filtering, skeletonization, and CCL algorithms are applied to masked wire-only images to segment nets. Hough transform priors (as in Masala-CHAI) enhance straight-line detection and cluster endpoints within geometric thresholds ([min ∥p_{i,k}-p_{j,l}∥₂ ≤ 40 px]) to unify wire segments as the same net (Bhandari et al., 2024).
• Pin-to-Net and Junction Detection: BFS-based expansion from component footprints, as in AMSNet, groups adjacent pixels as candidate nets; intersections are algorithmically resolved using convolution over binary wire masks to identify missing junctions (Tao et al., 2024). Ambiguities (e.g., odd-cluster groupings) are flagged for manual correction or downstream self-correction.
• OCR and Reference Assignment: Vision-LLMs, sometimes operating alongside EasyOCR and CNN feature extractors, map bounding-boxes to text annotations for reference designator retrieval, solved as a bipartite matching problem on similarity scores (Aldowaish et al., 29 Jan 2026).

3. Graph-Based Data Structures and Representation

The underlying circuit is formalized as a graph or hypergraph structure suitable for automated manipulation:

• Bipartite Graphs: AMSNet, SINA, and many contemporary datasets conceptualize the circuit as a bipartite graph $G = (C, N, E)$, with $C$ the component set, $N$ the net set (corresponding to wires and junctions), and $E$ the pin-to-net connections. Each component and net record encapsulates type, orientation, and parameter annotations (Tao et al., 2024, Aldowaish et al., 29 Jan 2026).
• Port-Level Graphs for AI Models: GNN-based approaches like GNN-ACLP encode each port as a node, with device class/terminaltype as categorical features, and explicit undirected edges representing electrical connectivity. The node-feature matrix and adjacency enable standard GNN message passing (Pan et al., 14 Apr 2025).
• Hierarchical JSON or Programmatic Representations: Differentiable programming frameworks represent each (sub)circuit as a module with explicit fields: “ExternalNodes,” “InternalNodes,” “InputParams,” “SubModel” (dynamic parameters, optional), and “Schematic” (the contained instances). The global netlist is then a map of module names to such dictionaries, facilitating parametric recursion, gradient propagation, and runtime re-evaluation (Long et al., 2024, Gutiérrez et al., 2023).
• Quantum Gate Sequences: For quantum netlists, a list of gate records ({type, qubits, parameter}) is maintained, applying staged decomposition, mapping, and optimization before formatted emission to OpenQASM (Aktar et al., 2022).

4. Net Naming, Pin Ordering, and Explicit Netlist Emission

A robust netlist requires canonical net naming and correct terminal ordering, with representations tailored to the simulation backend:

• Sequential Net Assignment: Nets are typically named in discovery order (“N0, N1, …”) or based on function (IN, OUT, VDD, GND, net_int_k), as dictated by their initial labels or type attributes (Uhlich et al., 2024, Tao et al., 2024).
• Pin Ordering Heuristics: Especially relevant for multi-terminal devices, pin ordering is resolved according to geometric angles (AMSNet), industry SPICE conventions (drain, gate, source, body for MOS), or explicit mapping from annotation or knowledge graph (Tao et al., 2024, Shi et al., 2024).
• Parameterization and Sizing: Default or dataset-supplied device dimensions (e.g., W₀=1 μm, L₀=0.18 μm in AMSNet) are utilized when not specified in the source. In auto-design, parameters may be optimized via Bayesian approaches (AMSnet-KG) and automatically propagated by insertion into emission templates (Shi et al., 2024).
• Netlist Formatting: Each component emits a standard SPICE (.sp) format or compatible representation:
  • For passive/active elements:

    R<id> <n_a> <n_b> R=<value> M<id> <d> <g> <s> <b> <model> W=<W_i> L=<L_i> X<id> <n₁> ... <n_k> <subckt> PARAMS: ...

  • For quantum circuits:

    openqasm 2.0; include "qelib1.inc"; [u3(θ, φ, λ) q[i]; cx q[i],q[j]; ...]

  • For programmatic or computational-graph-based frameworks, JSON or Python object hierarchies represent the network, to be flattened at export (Long et al., 2024, Gutiérrez et al., 2023).

5. Verification, Correction, and Dataset Construction

Netlist fidelity is assessed via algorithmic and learning-based verification, with several key approaches:

• Graph-Based Structural Verification: Post-construction, netlists are parsed back into their graph representations for validation. Graph Edit Distance (GED) metrics and floating net detection (isolated pins/nets) quantify structural correctness (Bhandari et al., 2024).
• Self-Correction Loops: In LLM-driven pipelines (Masala-CHAI), failed verifications prompt rapid self-correction using LLM feedback to fix floating nets or ambiguous mappings through iterative re-prompting (Bhandari et al., 2024).
• Manual and Automated Quality Control: Systems such as AMSNet blend high-throughput automation (fully automatic conversion for >97% of their 894 schematics) with targeted manual correction for flagged cases (odd-cluster nets, thresholded at <3%) (Tao et al., 2024).
• Evaluation Metrics: Published accuracy metrics include component detection mAP (SINA/AMSNet: >97%), net labeling accuracy (~96%), F1 scores, success rates (Masala-CHAI’s LLM achieves 100% similarity S on AMSNet after normalization for multiple tasks), Pass@1 (agentic LLM frameworks), and convergence statistics for optimization-driven frameworks (Tao et al., 2024, Aldowaish et al., 29 Jan 2026, Bhandari et al., 2024).
• Canonical Datasets: Annotated benchmarks (AMSNet, Masala-CHAI, SpiceNetlist, AMSnet-KG) provide paired schematic-netlist records, typically also including JSON metadata, schematic PNGs, and, when applicable, simulation testbenches (Tao et al., 2024, Bhandari et al., 2024, Pan et al., 14 Apr 2025, Shi et al., 2024).

6. Algorithmic and AI-Driven Advances

Recent research extends classical netlist construction with advanced algorithmic capabilities, AI-driven reasoning, and differentiable infrastructure:

• GNN-Based Topology Completion: GNN-ACLP’s SEAL pipeline reconstructs missing netlist links by encoding port-level features, subgraph descriptors (Double-Radius Node Labeling), and running message-passing GNNs followed by link-score decoding MLPs, achieving high cross-dataset transferability (Pan et al., 14 Apr 2025).
• LLM Pipelines: Agentic frameworks, such as AnalogCoder (using Masala-CHAI datasets), apply prompt-tuned, modality-bridged LLMs to directly translate annotated schematics to netlists, achieving dramatic improvements in Pass@1 and fine-tuning success rates, especially on structurally complex analog circuits (Bhandari et al., 2024).
• Graph Composer RL and Evolutionary Search: GraCo synthesizes netlist graphs step-by-step via RL, enforcing consistency checks during or after generation—yielding significantly higher sample-efficiency and Quality-of-Result metrics in both digital and analog domains. SpiceMixer augments this process with normalized netlist line-level crossover, mutation, and pruning operators, operating with standardized tokenization across homologous designs, leading to improved convergence and design diversity (Uhlich et al., 2024, Uhlich et al., 2 Jun 2025).
• Differentiable, Hierarchical Computational Graphs: Modern netlist formats embed computational graphs at the module level (nodes = subcircuits/devices), allowing signal/parameter dataflow and supporting full gradient propagation. JSON netlists with SubModel routines permit automatic top-down/bottom-up differentiation for auto-sizing, sensitivity analysis, and integration with ML toolchains (Long et al., 2024).
• Quantum Compilation: Quantum netlist construction decomposes arbitrary $U\in U(2^n)$ via Givens rotations, routes via shortest-path decomposition subject to hardware topology graphs, and emits OpenQASM circuits, incorporating both mapping and basic gate-level optimization (Aktar et al., 2022).

7. Domain-Specific Extensions and Field-Circuit Integration

Netlist construction is generalized beyond classical SPICE-like tasks in several advanced contexts:

• Electrothermal/Electromagnetic Field Problems: FIT-based approaches discretize 3D domains onto primal/dual grids, mapping system matrices (conductance, capacitance, permeability) to equivalent netlist elements (R, C, L, behavioral sources), including specialized stamps for absorbing boundary conditions (Engquist–Majda), enabling high-fidelity field–circuit simulations without custom integrators (Casper et al., 2018).
• Hierarchical/Parametric Generation: Python object-oriented frameworks support modular and parameterized netlist construction, using core abstractions (Component, ParamSet, Manip, Subcircuit, Circuit, Exporter) to build and emit simulator-ready SPICE from symbolic descriptions. Parameter values can be random variables, symbolic expressions, or externally read PDK/Verilog-A/JSON imports (Gutiérrez et al., 2023).
• Auto-Design and Knowledge Graphs: Integration of structured knowledge graphs facilitates pin-aware topology assembly, constraint-augmented search, and iterative topology refinement in LLM-driven auto-design. The use of chain-of-thought LLM prompting to extract design strategies, followed by query-constrained component retrieval and parametric synthesis, realizes closed-loop, specification-driven netlist generation (Shi et al., 2024).

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• (Tao et al., 2024) AMSNet: Netlist Dataset for AMS Circuits
• (Pan et al., 14 Apr 2025) GNN-ACLP: Graph Neural Networks based Analog Circuit Link Prediction
• (Aldowaish et al., 29 Jan 2026) SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence
• (Bhandari et al., 2024) Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
• (Shi et al., 2024) AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG
• (Uhlich et al., 2024) GraCo -- A Graph Composer for Integrated Circuits
• (Long et al., 2024) Computational Graph Representation of Equations System Constructors in Hierarchical Circuit Simulation
• (Uhlich et al., 2 Jun 2025) SpiceMixer -- Netlist-Level Circuit Evolution
• (Gutiérrez et al., 2023) Python Framework for Modular and Parametric SPICE Netlists Generation
• (Casper et al., 2018) Automated Netlist Generation for 3D Electrothermal and Electromagnetic Field Problems
• (Aktar et al., 2022) Quantum Netlist Compiler (QNC)