CircuitLM: LLM-Driven Circuit Synthesis

Updated 15 January 2026

CircuitLM is a framework that combines LLM-powered multi-agent pipelines with the Electronic Circuit Model to translate natural language into machine-enforceable circuit schematics.
It employs embedding-driven retrieval, agentic reasoning, and formal electrical analogies to bridge the semantic gap between human intent and hardware design.
Evaluation via Dual-Metric Circuit Validation demonstrates high schema compliance and logic accuracy, underscoring its potential for rapid prototyping and educational applications.

CircuitLM defines a set of conceptual, algorithmic, and practical advances in LLM-driven electronic circuit synthesis and understanding. It refers both to a multi-agent pipeline for translating natural language prompts into machine-enforceable schematics (Hasan et al., 8 Jan 2026), and a unified mathematical abstraction—also termed the Electronic Circuit Model (ECM)—for quantitatively predicting LLM accuracy from in-context learning (ICL) and chain-of-thought (CoT) prompting (Chen et al., 5 Feb 2025). CircuitLM integrates embedding-driven retrieval, agentic reasoning decomposition, and formal electrical analogy to bridge the semantic gap between human intent and deployable hardware designs.

1. CircuitLM Mathematical Framework: Electronic Circuit Model

CircuitLM models LLM reasoning as an electronic circuit, mapping prompt and inference structures onto physical quantities:

Model-Inherent Capability (Voltage Source): The base LLM skill, encoded as fixed voltage $E_{model}$ .
In-Context Learning (Semantic Magnetic Field): Few-shot demonstrations induce an electromotive force per Faraday’s Law:

$E_{ICL} = \lambda\,\sum_{i=1}^N \frac{S_q\cdot S_i}{\|S_q\|}$

where $S_q$ is the embedding of the query, $S_i$ that of the $i$ -th demonstration, and $\lambda$ a decay constant.

Chain-of-Thought Reasoning (Series Resistances): Each sub-step contributes a resistance $R_i$ ; the total is $R_{CoT} = \sum_{i=1}^K R_i$ .
Overall Output Power (Accuracy Prediction):

$P_{out} = \frac{(E_{model}+E_{ICL})^2 R_0}{(R_{CoT}+R_0)^2}$

where $R_0$ is the fixed ‘decision’ overhead.

Empirically, $P_{out}$ tracks task accuracy linearly with Spearman $\rho\approx 0.88-0.91$ across 13 models, diverse prompts, and benchmarks (Chen et al., 5 Feb 2025).

2. Multi-Agent Pipeline for Prompt-to-Schematic Generation

CircuitLM implements prompt-to-circuit translation using a cascade of five LLM-aided agents (Hasan et al., 8 Jan 2026):

Component Identification: LLM-based NER extracts generic component names from the prompt.
Component Matching (Knowledge Retrieval):
- Embedding-indexed ChromaDB anchors each part to canonical pinouts, using Qwen3 embeddings and cosine similarity plus fuzzy alias lookup: $\mathrm{sim}(v_q, v_d) = \frac{v_q \cdot v_d}{\|v_q\|\|v_d\|}$ .
Electronics Expert (Chain-of-Thought Reasoning): Structured CoT trace hierarchically decomposes all required connections, including safety, power rails, and logic.
Circuit Generation: Machine-readability enforced via the CircuitJSON schema; explicit (x,y) placements, pin-validated nets, connectivities.
Force-Directed SVG Visualization: Schematic is rendered using Fruchterman–Reingold layout and Manhattan wire-routing. Repulsive and attractive forces governed by

$f_r(d_{ij}) = -\frac{k^2}{d_{ij}}, \qquad f_a(d_{ij}) = \frac{d_{ij}^2}{k}$

with minimization over path length, bend count, and crossings.

3. Validation, Evaluation Metric, and Database-Driven Safety

Safety and fidelity are assessed using the Dual-Metric Circuit Validation (DMCV) framework, which blends library compliance and electrical logic:

Library Compliance:

$S_{\mathrm{comp}} = \max\left(0, \frac{100 - 10n_s - 5n_p}{10}\right)$

penalizing missing/wrong pins and net assignments.

Electrical Logic:

$S_{\mathrm{logic}} = \mathrm{clip}\left(10 - 2.0 n_f - 1.0 n_m - 0.5 n_{mi} - 0.25 n_w, 0, 10\right)$

scoring fatal, major, minor errors, and warnings.

Aggregate Metric:

$S_{\mathrm{DMCV}} = 0.6 S_{\mathrm{logic}} + 0.4 S_{\mathrm{comp}}$

Evaluations with six LLMs over 100 prompts show library compliance nearly perfect ( $\mu\approx9.9$ ); logic scores vary with reasoning ablations (Hasan et al., 8 Jan 2026).

4. CircuitJSON: Structured Schematic Representation

CircuitLM introduces CircuitJSON, a strict schema for circuit encoding:

{
  "version": "1.0",
  "author": "agent-id",
  "parts": [{"type":"arduino-uno","id":"U1","left":100,"top":200,"attrs":{"footprint":"TQFP-32"},"rotate":0}],
  "connections":[{"startPin":"U1:5V", "endPin":"LED1:A", "color":"red", "route":["H","V","H"]}]
}

Schema enforcement guarantees pin-existence, net-uniqueness, and downstream tool compatibility.

5. Experimental Results and Ablation Studies

Component Database: 50 parts, extensible by embedding metadata and aliases.
Dataset: 100 diverse prompts spanning microcontroller, bus, and sensor circuits.
Models Evaluated: GPT-5-Mini, Gemini-2.5-Flash, Deepseek-v3.1, Qwen3-235B, Grok-Code-Fast, Llama-3.3-70B.
Aggregate Performances:
- Highest $S_{\mathrm{DMCV}}=8.503$ (Gemini 2.5 Flash), lowest $7.865$ (Llama-3.3).
- CoT-stage ablation effect is mixed: logic scores rise or fall depending on model.
Human Expert Validation: DMCV scores are consistent with manual reviews on 25% samples.

6. Limitations, Generalization, and Future Directions

Latency: Multi-agent round trips introduce inference delays; future versions may use on-device quantized agents.
Database Extensibility: Schema and retrieval pipeline can accommodate new parts by updating embeddings.
Evaluation Bias: Single-model scoring is planned to evolve to a consensus, cross-ensemble QA.
EDA Integration: Absence of SPICE/netlist stages places CircuitLM as a prototyping/educational tool; ERC and SPICE-backed flows are future extensions.
Planned Innovations:
- Evaluation-Feedback-in-the-Loop (EFIL) iterative repair
- Heterogeneous agent mix (reasoning versus schema generation)
- Cross-model logic cross-checking.

A plausible implication is that by anchoring all wiring and logic in a pin-enforced embedding database and hybrid evaluation, the probability of subtle electrical errors and hallucinations is reduced relative to prior monolithic LLM workflows.

7. Relationship to Analog Schematic Understanding and Broader EDA Pipelines

CircuitLM’s agentic decomposition is orthogonal and complementary to analog circuit understanding frameworks such as TopoSizing (Wei et al., 17 Sep 2025) and AmpAgent (Liu et al., 2024). TopoSizing employs hierarchical graph encoding of SPICE netlists, module-stage abstraction, iterative hypothesis-verification-refinement, and LLM-seeded Bayesian optimization; AmpAgent orchestrates RAG-based literature parsing, algebraic reasoning, and device sizing agents to accelerate amplifier synthesis. Editor's term: "Agentic Circuit Design" denotes this multi-agent, retrieval-driven, and verification-laden approach.

CircuitLM, in this context, exemplifies the tendency toward modular, formalized, and extensible pipelines in circuit EDA, where semantic fidelity and hardware deployability are ensured by embedding-driven part selection, agent-enforced reasoning, and explicit schema constraints (Hasan et al., 8 Jan 2026, Chen et al., 5 Feb 2025).