Minimum ancilla count for flag-based verification circuits

Determine the minimal number of ancilla flag qubits required to synthesize a verification circuit that flags all harmful errors for a given non-fault-tolerant logical state preparation circuit U of a specified stabilizer code [[n,k,d]], under a specified native gate set and qubit connectivity. In particular, ascertain conditions under which a solution exists for a given ancilla budget and develop a priori criteria to decide the necessary ancilla count before circuit synthesis.

Background

The paper introduces a reinforcement learning approach to synthesize verification circuits that use ancilla flag qubits to render a given non-fault-tolerant logical state preparation circuit fault-tolerant. These flag qubits are intended to signal harmful error events so runs with triggered flags can be discarded while preserving the logical state.

A practical challenge highlighted by the authors is that, for a fixed encoding circuit U and error model, the number of ancilla flag qubits needed to guarantee that all harmful errors are flagged is not straightforward to determine beforehand. This uncertainty impacts both resource allocation and the training workflow, as they begin with one flag qubit and increment the number until a satisfactory solution is discovered.

Resolving this question would enable principled a priori resource planning, reduce search effort, and provide guarantees for feasibility under connectivity and gate-set constraints.