Optimality and additive depth scaling for approximate unitary designs
Determine whether ε-approximate unitary k-designs over n qubits with relative error can be generated in circuit depth O(k) + O(log(n/ε)), rather than requiring a multiplicative scaling in k and log(n/ε) as in current constructions, and establish matching upper and lower bounds on the minimal circuit depth as a function of all three parameters n, k, and ε.
References
On the mathematical side, an obvious open question concerns the optimality of our unitary design construction. While we have proven in Proposition~\ref{prop: lower bound design} that our $n$-dependence is optimal, and we inherit the optimal $k$-dependence of Ref. up to poly-logarithmic factors, the relation between these two dependencies is not known. More precisely, we cannot yet rule out the possibility that $\varepsilon$-approximate unitary $k$-designs over $n$ qubits can be created in depth $\mathcal{O}(k) + \mathcal{O}(\log(n / \varepsilon))$, whereas our construction requires a depth of $\tilde{\mathcal{O}(k) \times \mathcal{O}(\log(n / \varepsilon))$. Achieving a matching upper and lower bound on the circuit depth with respect to all three parameters $n, k, \varepsilon$ remains an outstanding challenge.