View-Consistent Colorization

• View-Consistent Colorization is a method ensuring that multiple views of a scene maintain uniform and coherent color representation.
• It leverages advanced algorithms and machine learning models to minimize color shifts and enhance perceptual realism.
• Widely applied in video restoration, multi-view imaging, and 3D reconstructions, it significantly improves visual fidelity.

A single-photon avalanche diode (SPAD) array is a two-dimensional or one-dimensional grid of digitally operated avalanche photodiodes, each acting as an independent photon counter with picosecond timing and single-photon sensitivity. These arrays combine a reverse-biased p–n junction detector with closely integrated digital logic, enabling time-resolved, photon-number resolved, and spatially multiplexed measurements for photon-starved applications across quantum optics, time-of-flight (ToF) depth imaging, biophotonics, and advanced microscopy. The architecture capitalizes on advancements in CMOS device scaling, device physics, and microelectronics to realize scalable, low-noise, and high-timing-resolution detector arrays for scientific and emerging commercial domains.

1. Device Physics and Array Design Principles

A SPAD pixel is a p–n (or p–i–n, n–i–p) diode reverse-biased above its breakdown voltage (Geiger mode), so that a single photo-generated carrier can initiate a self-sustaining avalanche. The key features of SPAD array design include:

• Active Quenching and Recharge: Upon avalanche onset, a fast circuit rapidly quenches the current by dropping the bias below breakdown, then recharges the junction to restore sensitivity. Dead time per pixel ranges from a few ns (state-of-the-art) to hundreds of ns in older or mission-specific designs (Wang et al., 2023, Sieleghem et al., 2021).
• Pixel Structure: The photosensitive area (active diameter 2–50 μm) is surrounded by guard rings and deep trenches to prevent edge breakdown and suppress optical/electrical crosstalk (Gulinatti et al., 2020, Sieleghem et al., 2021). A spherically uniform electric field profile can be engineered to maximize gain and timing uniformity (Sieleghem et al., 2021, Sieleghem et al., 2022).
• Fill Factor: Geometric fill factor is the ratio of the SPAD’s sensitive area to the pixel pitch, often as low as 3–10% in standard digital arrays due to the area required for quench logic and per-pixel counters (Wang et al., 2023, Ma et al., 2020). Advanced designs recover up to 80% with microlenses, backside illumination (BSI), or charge-focusing architectures (Sieleghem et al., 2022).
• Monolithic Integration: SPADs are fabricated in standard or specialized CMOS flows, allowing for monolithic cointegration of quenching, TDC, and digital readout logic underneath or alongside the SPAD (Tétrault et al., 2014, Wang et al., 2023, Gulinatti et al., 2020).
• Scalability: Arrays range from 8×8 pixels for embedded sensing (Zang et al., 2024) to megapixel imaging formats (Bian et al., 2022, Defienne et al., 2020). High pitch (≥150 μm) arrays are typical for quantum sensing; aggressive scaling (down to 10–15 μm) is available for imaging and ToF (Sieleghem et al., 2022, Bian et al., 2022).

2. Performance Metrics, Noise, and Crosstalk

The physical and electronic noise sources, as well as key performance metrics, are tightly coupled with device architecture and array scaling:

Parameter	Typical Value/Range	Comments
Photon Detection Efficiency (PDE)	20–70% (visible), 10–30% (NIR), up to 50% with BSI/microlenses	Product of quantum efficiency, fill factor, and avalanche probability (Gulinatti et al., 2020, Wang et al., 2023, Sieleghem et al., 2022)
Timing Jitter	30–300 ps FWHM	Device and readout limited; 50–100 ps with optimized profiles (Tétrault et al., 2014, Sieleghem et al., 2021, Gulinatti et al., 2020)
Dark Count Rate (DCR)	100–10,000 cps/pixel	Exponential dependence on temperature and bias; sub-100 cps in cooled or optimized devices (Wang et al., 2023, Gulinatti et al., 2020)
Afterpulsing	<0.1%–2% per event	Reduced by small active volume, active quench, longer hold-off (Sieleghem et al., 2021, Gulinatti et al., 2020)
Optical/Electrical Crosstalk	<0.1–5% (nearest neighbor)	Suppressed by pitch, trenches, and gating (Lubin et al., 2019, Wang et al., 2023, Dolphin et al., 5 Sep 2025)
Dead Time	1–100 ns	Determines max per-pixel count rate; GHZ gating for InGaAs/InP (Wang et al., 2023, Dolphin et al., 5 Sep 2025)

The contribution of each noise source is well modeled by:

$$N = N_\mathrm{shot} + N_\mathrm{fp} + N_\mathrm{dark} + N_\mathrm{ap} + N_\mathrm{ct} + N_\mathrm{dt}$$

where these represent photon shot noise, fixed-pattern gain, dark count, afterpulsing, crosstalk, and dead time exclusion (Bian et al., 2022).

3. Readout Architectures and Data Processing

SPAD arrays employ a range of readout schemes, optimized for application bandwidth, timing resolution, and energy efficiency:

• Fully Digital Embedded Readout: Real-time, 3D-stacked digital engines with per-pixel timing, energy summation, and event packaging directly under the sensitive layer, virtually eliminating the fill factor vs. capability trade-off (Tétrault et al., 2014). For example, each of a 22×22 sub-matrix can have an independent quench/TDC path and 64-word dual buffer (Tétrault et al., 2014).
• Global/Asynchronous Gating: Entire arrays may be switched synchronously (global shutter) for time-of-arrival histogramming; or per-pixel gating is used for dynamic scenes and background mitigation (Wang et al., 2023, Scholes et al., 2022).
• On-Pixel Counters and TDCs: Each pixel may incorporate one or more LFSR counters for photon counting or 50–200 ps TDCs for precise time stamping, with digital output only (Wang et al., 2023, Bian et al., 2022, Sieleghem et al., 2022). In some designs, TDCs and counters are multiplexed column-wise to save area; in 3D-stacked chips, TDCs reside on a logic tier (Bruschini et al., 2019).
• Data Reduction: Hierarchical buffering and in-pixel/event-based local processing (including real-time discrimination and histogramming) can reduce off-chip data by 8-fold or more (Tétrault et al., 2014, Wang et al., 2023, Afshar et al., 2019). Real-time suppression of dark counts and failed events further limits power and bandwidth.
• Neuromorphic/Event-Based Processing: Some architectures implement local pooling, feature extraction, or winner-take-all logic at the array periphery or even intra-pixel, enabling event-driven data output that is orders-of-magnitude smaller than raw frames and with higher downstream utility (Afshar et al., 2019). These methods have been shown to yield >81× bandwidth reduction and improved recognition accuracy in high-speed, noisy recognition tasks.

4. Application Domains

SPAD arrays have enabled advances in domains that require single-photon sensitivity, fast timing, and large-area or parallelized multiplexing:

• Time-of-Flight PET (Positron Emission Tomography): Vertically stacked, digital readout architectures with first-photon discrimination and 31 ps TDCs enable sub-200 ps coincidence timing and low dead time for high-resolution PET, with data reduction achieving up to 8× reduction and multi-MCPS throughput (Tétrault et al., 2014).
• Wide-Field Quantum Sensing and Imaging: High frame-rate SPAD matrices (e.g., 64×32, 2048 pixels) linked to NV–diamond systems or entangled light, with per-pixel gating, allow for 100 kHz parallel scanning, supporting high-speed AC/DC field mapping, quantum correlation, and full-field quantum microscopy with robust optical noise rejection (Wang et al., 2023, Defienne et al., 2020, Lubin et al., 2019).
• Compressive Raman and Spectral Imaging: Linear SPAD arrays (e.g., 512-channel) support high SNR and throughput in compressive Raman schemes, reducing per-point integration to ~23 μs and increasing volumetric speed by >10× vs. single-pixel approaches (Gentner et al., 2023).
• Super-Resolution and Event-Based Microscopy: Asynchronous, high-fill-factor arrays with sub-100 ps timing and integrated feature extraction enable ISM and Q-ISM, pushing spatial resolution up to ×2 over the diffraction limit and supporting photon-number-resolved imaging in microscope modalities (Buttafava et al., 2020, Lubin et al., 2019).
• Emerging SNN and Event-Driven Recognition: Embedding Poisson-driven photon count data from low-cost 8×8 SPADs into SNNs and other neuromorphic architectures supports robust, low-power pattern extraction under low light and high noise, with accuracy competitive with frame-based CNNs (Zang et al., 2024, Afshar et al., 2019).

5. Strategies for Noise Mitigation, Fill Factor, and Scalability

Several techniques have been adopted to address the intrinsic and extrinsic limitations of SPAD arrays:

• Active Quenching and Hold-Off Optimization: Reduces afterpulsing to <0.1%, supports count rates up to 20 Mcps/pixel with minimal timing skew (Wang et al., 2023, Sieleghem et al., 2021).
• Deep-Trench and Charge-Focusing Isolation: Full dielectric or heavily-doped trench isolation, alongside charge-focusing geometries (spherically uniform field peaks), suppress both crosstalk and edge breakdown, enabling pitch scaling below 15 μm and fill factors beyond 70% (Gulinatti et al., 2020, Sieleghem et al., 2022, Sieleghem et al., 2021).
• Microlenses and BSI: Micro-optics and backside-illumination can increase effective fill factor from <5% to >70%; BSI with metal reflectors further enhances NIR PDE (Wang et al., 2023, Sieleghem et al., 2022, Bian et al., 2022).
• 3D-Stacking: Separating the photosensitive and electronics tiers via through-silicon vias enables high fill factor and density, with on-chip intelligent data processing (Tétrault et al., 2014, Bruschini et al., 2019).
• Scaling Arrays for Application-Specific Needs: Pixel and array geometries are adapted for application (e.g., 8×8 for embedded ToF, 512×512 for quantum imaging), with careful optimization of quench and readout logic to balance PDE, timing, and data rate (Wang et al., 2023, Bian et al., 2022, Gulinatti et al., 2020).

6. Future Outlook and Research Directions

Proposed advances and envisioned developments focus on breaking current trade-offs in pixel pitch, timing, PDE, and on-chip processing:

• Pixel Miniaturization & Megapixel Arrays: Reduction to sub-10 μm pitch using advanced CMOS and BSI with near-unity fill factor is projected, supporting multi-megapixel, sub-50 ps jitter, and high PDE devices (Bian et al., 2022, Sieleghem et al., 2022, Bruschini et al., 2019).
• Integrated Per-Pixel TDCs and Computation: The integration of per-pixel, sub-20 ps TDCs, local counters, and event-processing logic promises massive parallelization for ToF, lifetime, and quantum information imaging (Wang et al., 2023, Tétrault et al., 2014).
• 3D-Stacked and Multimaterial Architectures: Hybrid InGaAs/InP SPADs extend spectral reach to telecom; three-dimensional integration decouples fill factor from logic area, with potential for hybrid and heterogenous PIC/SPAD systems (Dolphin et al., 5 Sep 2025, Gualandi et al., 6 Dec 2025, Sieleghem et al., 2021).
• Neuromorphic and Event-Driven Readouts: Event-based architectures at pixel, block, or column-level are poised to minimize output data bandwidth, reduce power, and support embedded, always-on, decision-making sensors (Afshar et al., 2019, Zang et al., 2024).
• Deep Learning Post-Processing: SPAD-tailored, transformer-based super-resolution can enhance imaging quality, overcoming hardware limitations in array pitch and bit depth, pushing SPAD arrays into more general imaging domains (Bian et al., 2022).
• Low-Temperature, Low-Noise, and High-Speed Operations: Further noise reduction, GHz gating for telecom and quantum communication, and ultrafast frame rates (up to 1 MHz) remain under active development, targeting new applications in quantum information, LiDAR, and advanced microscopy (Dolphin et al., 5 Sep 2025, Defienne et al., 2020).

7. Comparative Landscape and Domain-Specific Implementations

SPAD arrays stand apart from CCDs/CMOS sensors and traditional PMT/SiPM detectors in their:

• Native digital output with zero read noise,
• Sub-nanosecond temporal precision,
• Single-photon sensitivity at room temperature,
• Scalability to high pixel counts and dense logic integration,
• Flexible, event-driven data output and massive parallelization.

Table: Representative SPAD Array Metrics (selected examples)

Sensor	Pixels	Fill Factor [%]	PDE (Peak/λ)	DCR [cps/pixel]	Timing Jitter [ps]	Application Domain	Reference
MPD-SPC3	64×32	3/(78)	50%@410nm	100	100–200	Quantum Sensing, NV centers	(Wang et al., 2023)
Custom RE-SPAD	32×1	7.8	70%@650, 45%@800	3,000	95	Quantum Optics, LiDAR	(Gulinatti et al., 2020)
Hybrid InGaAs/InP	1×4	50	16%@1550nm	<8,000	50–70	QKD	(Dolphin et al., 5 Sep 2025)
SwissSPAD2	512×512	10.5	25%@700nm	7	<40	Full-Field Quantum Imaging	(Defienne et al., 2020)
Polimi/IMM-CNR (PIC coupled)	8×8	—	50%@561nm	2,900–16,600	—	Quantum Photonics, PIC	(Gualandi et al., 6 Dec 2025)

SPAD arrays have established themselves as the enabling platform for single-photon-level imaging and timing in contemporary and next-generation quantum science, biophotonics, time-resolved imaging, and photonic information processing, with ongoing research focused on further integrating intelligence, sensitivity, and scalability at the pixel and system level.