Single-Photon Avalanche Diodes (SPADs)

• SPADs are semiconductor photodetectors that operate above breakdown voltage (Geiger mode) to digitally detect single photons with high sensitivity.
• They employ specialized architectures like Si, InGaAs/InP, and CMOS-integrated arrays to optimize photon detection efficiency, timing jitter, and dark count rate.
• Applications of SPADs span quantum optics, time-of-flight imaging, LiDAR, and integrated photonic circuits, advancing both research and commercial imaging.

A single-photon avalanche diode (SPAD) is a semiconductor photodetector engineered to enable digital detection of single photons in the visible, near-infrared, or short-wavelength infrared spectral regimes. SPADs are reverse-biased p–n, p–i–n, or heterojunction diodes, operated above breakdown (“Geiger mode”) so that the absorption of a single photon can trigger a self-propagating avalanche of charge carriers, resulting in a macroscopic current pulse that is quenched and detected by supporting electronics. SPADs have become central to diverse scientific and technological domains including quantum optics, time-of-flight imaging, quantum key distribution, time-resolved spectroscopy, ultra-low-light and high-dynamic-range imaging, and emerging quantum information processing platforms.

1. Physical Principles and Device Architectures

A SPAD is fundamentally a photodiode reverse-biased such that the electric field in the multiplication (avalanche) region exceeds a critical threshold, allowing impact ionization by photogenerated or thermally generated carriers. In Geiger mode, after the avalanche is triggered, the device is quickly quenched and reset to prevent catastrophic breakdown, with the dead time imposed by quenching and recharge limiting the maximum count rate (An et al., 24 Jul 2025, Yu et al., 2024, Suonsivu et al., 19 Jan 2026, Hernandez et al., 2017).

Key Device Types:

• Silicon SPADs (Si SPADs):

Dominant for the visible and near-infrared. Structures encompass thick-junction, reach-through, and nanostructured architectures. Thick-junction back-illuminated Si SPADs can achieve PDE >84% at 785 nm by leveraging deep absorption layers for near-unity quantum efficiency and enhanced electron-initiated avalanche probability (An et al., 24 Jul 2025, Stipčević et al., 2013).

• InGaAs/InP SPADs:

Extend sensitivity to 1.0–1.7 μm. Employ a Separate Absorption, Grading, Charge, and Multiplication (SAGCM) structure, optimizing PDE, DCR, and afterpulsing by balancing field distributions, compositional grading, and charge control (Yu et al., 2024, Ma et al., 2016).

• Ge–Si Heterojunction SPADs:

CMOS-compatible extension into the SWIR, using a Ge absorption layer and Si avalanche region for room-temperature ≤12% PDE at 1.31 μm (Na et al., 2024). Waveguide-integrated GeSi SPADs have been demonstrated, achieving system-level performance competitive with SNSPDs in temporally gated architectures (Na et al., 2024).

• CMOS SPAD Arrays and Photonic Integration:

Standard CMOS processes allow large SPAD arrays for imaging, biophotonics, quantum imaging, and on-chip quantum photonics. Monolithic photonic integration (e.g., waveguide-coupled Si or GeSi SPADs) enables dense, scalable photonic systems (Govdeli et al., 2023, Bruschini et al., 2019).

SPAD performance is set by absorption efficiency, avalanche probability (field profile and excess bias), device geometry (absorption and multiplication thickness, junction type), quenching electronics, and the suppression of non-idealities such as defect-induced dark current, afterpulsing, and crosstalk (An et al., 24 Jul 2025, Yu et al., 2024, Stipčević et al., 2013, Ma et al., 2015).

2. Fundamental Performance Metrics

The parameters that define SPAD performance are tightly coupled and often present trade-offs:

• Photon Detection Efficiency (PDE):

Probability that an incident photon generates a detectable avalanche. Decomposed as

$$PDE(\lambda, V_{ex}) = \eta_{abs}(\lambda) \cdot P_{a}(V_{ex}) \cdot \eta_{coll}$$

where $\eta_{abs}$ is absorption probability, $P_a$ the avalanche probability dependent on field and excess bias $V_{ex}$, and $\eta_{coll}$ collects geometric and coupling losses (An et al., 24 Jul 2025).

• Dark Count Rate (DCR):

Rate of avalanches in complete darkness, stemming from thermal generation, tunneling, and defect states. Expressed as

$$DCR \propto \exp\left( -\frac{E_g}{2 kT}\right) \cdot \exp(c V_{ex})$$

with both thermal and field-enhanced components (An et al., 24 Jul 2025, Yu et al., 2024).

• Timing Jitter:

Uncertainty in photon-arrival to avalanche timestamp. Contributions from carrier transit-time spread, avalanche build-up statistics, and electronic response. FWHM values can be as low as 10 ps (waveguide Si SPADs), 22 ps (CMOS SPADs for MIP detection), or 150–400 ps in thick, high-PDE Si SPADs (Gramuglia et al., 2021, An et al., 24 Jul 2025, Ma et al., 2015, Yanikgonul et al., 2019).

• Afterpulsing Probability:

Fraction of detections correlated with preceding avalanches, caused by release of trapped carriers.

$$P_{ap} \propto (\text{charge per avalanche}) \times (\text{trap density}) \times (\text{hold-off time}^{-1})$$

(An et al., 24 Jul 2025, Yu et al., 2024).

• Maximum Count Rate and Dead Time:

Determined by the recharge/quenching mechanism. Short dead times (≤10 ns) and fast active quench circuits favor high count rates (>10–100 Mcps) (An et al., 24 Jul 2025).

Achieving high PDE typically requires operating at high excess bias, but this also increases DCR and afterpulsing, so device and circuit design must be optimized for application-specific requirements (An et al., 24 Jul 2025, Yu et al., 2024, Stipčević et al., 2013).

3. Device Engineering and Noise Suppression

Device architectures and process optimizations target noise minimization, quantum efficiency enhancement, and timing performance:

• Backside Illumination:

Si SPADs with thick absorption layers and backside entry maximize electron-initiated avalanches. Electron ionization coefficient $\alpha_e \gg \alpha_h$ for Si, resulting in higher $P_a$ than traditional structures (An et al., 24 Jul 2025).

• Doping-Compensated Avalanche Regions:

Two-step boron–phosphorus diffusion pushes the high-field zone deeper into low-defect silicon, suppressing trap-assisted tunneling and reducing DCR and afterpulsing at high PDE (An et al., 24 Jul 2025).

• Nanophotonic Absorption Enhancement:

Antireflection and light-trapping nanocone gratings engineered above/below the absorption region enable >60% broadband QE in thin Si, decoupling timing jitter from absorption length (Ma et al., 2015).

• SAGCM Heterostructure:

In InGaAs/InP SPADs, compositionally graded interfaces, guard rings, field plates, and passivation reduce premature edge breakdown, surface leakage, and trap densities. Multiplication and absorption thicknesses are optimized for PDE/DCR/jitter trade-offs (Yu et al., 2024, Ma et al., 2016).

• Quenching and Gating Circuits:

High-voltage, actively controlled quenching circuits (up to 50 V, with inductive bootstrapping) enable fast, low-overhoot quench and short dead times. Operation in free-running, synchronous gating, or hybrid mode addresses afterpulsing and background suppression (An et al., 24 Jul 2025, Yu et al., 2024).

Engineering the field profile, interface quality, and passivation at the device level, and designing bespoke quenching and readout circuits at the module level, are critical to performance (An et al., 24 Jul 2025, Ma et al., 2015, Yu et al., 2024).

4. Applications and Integration

SPADs underpin a broad spectrum of scientific and industrial applications:

• Time-Correlated Single-Photon Counting (TCSPC):

Core technique in fluorescence lifetime imaging (FLIM), super-resolution microscopy, and time-resolved spectroscopy. SPAD arrays with per-pixel TDCs have enabled video-rate FLIM and ultrafast, high-dynamic-range imaging (Bruschini et al., 2019, Ma et al., 2020).

• Time-of-Flight Imaging / LiDAR:

Deep-Junction, NIR-enhanced, and InGaAs SPADs support ranging and 3D imaging in automotive, robotics, and geospatial applications. Sub-100 ps timing, high PDE, and low DCR are required for high-precision applications (Gramuglia et al., 2021, Sieleghem et al., 2021).

• Quantum Communications and QKD:

InGaAs/InP and GeSi SPADs at telecom wavelengths offer room-temperature operation, high system PDE, and low DCR as required for quantum key distribution over fiber and free-space links (Yu et al., 2024, Ma et al., 2016, Na et al., 2024, Na et al., 2024).

• Integrated Photonics and Quantum Photonic Circuits:

Waveguide-coupled Si and GeSi SPADs enable monolithic integration with photonic circuits, supporting on-chip quantum computing, photon-number-resolving detection (PNRD), and scalable quantum photonic processors (Govdeli et al., 2023, Yanikgonul et al., 2019, Na et al., 2024).

• Single-Photon Imaging and Computational Photography:

SPAD arrays (512×512 and beyond) facilitate passive and active single-photon imaging, quanta burst photography, and ultra-high dynamic range (HDR) imaging, outperforming CMOS/CCD sensors under low-light and fast-motion conditions (Ma et al., 2020, Ingle et al., 2019, Suonsivu et al., 19 Jan 2026).

• Quantum Imaging and Correlation Sensing:

Multi-pixel SPAD arrays allow measurement of higher-order photon correlations, Hanbury Brown–Twiss interferometry, quantum image scanning microscopy, and full-field quantum illumination (Lubin et al., 2019, Defienne et al., 2020).

In all these contexts, optimized SPADs (high PDE, low DCR/afterpulsing/jitter) and advanced readout circuits and architectures (e.g., per-pixel TDCs, event-driven logic, gating) are leveraged to internalize quantum noise limits and support application-specific performance (Bruschini et al., 2019, An et al., 24 Jul 2025, Yu et al., 2024).

5. Challenges, Trade-Offs, and Mitigation Strategies

SPAD operation and device scaling are constrained by several interrelated mechanisms:

• DCR increases sharply with $V_{ex}$ and temperature; this limits practical single-photon sensitivity, especially at room temperature or under radiation exposure. Mitigation includes device cooling, defect passivation, and optimized field engineering. Proton irradiation can induce defect-related DCR increases, but DCR can be partially mitigated via annealing, cooling, or disabling hot pixels (Campajola et al., 2022).
• Afterpulsing is exacerbated by deep traps, high charge flow, and short dead times. Short, high-amplitude quenching and deliberate dead time extension reduce afterpulsing rate but limit maximum count rates.
• Timing Jitter is minimized by ensuring rapid, drift-dominated transport into the avalanche region and by reducing lateral diffusion and field non-uniformity. Nanostructured absorption enhancement decouples absorption depth from jitter, enabling both high PDE and low jitter in thin devices (Ma et al., 2015).
• Trade-off between area and DCR: Large-area SPADs deliver high fill factor and ease of coupling but suffer increased DCR. Scaling to large arrays relies on crosstalk mitigation (deep trench isolation), per-pixel calibration, and robust event-logic (Lubin et al., 2019, Defienne et al., 2020).
• Radiation Hardness: In high-energy environments, displacement damage degrades DCR. Device design, process controls, and operational modalities (coincidence gating, annealing, cooling) sustain viability in radiation-affected missions (Campajola et al., 2022).

Emerging architectures, including 3D stacking, back-side illumination, and monolithic photonic integration, continue to address these trade-offs and constraints (Bruschini et al., 2019, Govdeli et al., 2023, Na et al., 2024).

6. Outlook and Future Directions

Current research targets the simultaneous optimization of PDE (>84% Si, >60% InGaAs/InP), DCR (<100 cps), timing jitter (<30 ps), afterpulsing (<1%), and count rates (>100 Mcps) across visible, NIR, and SWIR SPADs (An et al., 24 Jul 2025, Yu et al., 2024, Na et al., 2024). Key future directions include:

• Material and Interface Engineering:

Further reduction of trap densities, optical absorption extension for Si (via nanophotonics or heterojunctions), and compositional grading to support new spectral regimes.

• Integration of On-Chip Quenching and Logic:

Full CMOS/ASIC quenching for high pixel densities, per-pixel time-domain or event-driven logic, and scalable photon-number resolution.

• Array Scaling and Crosstalk Suppression:

Deep trench isolation, 3D stacking, high-fill-factor microlensing, and hybrid architectures for megapixel quantum imaging and parallel quantum information detection (Defienne et al., 2020, Bruschini et al., 2019).

• Cryogenics-Free Quantum Photonics:

GeSi SPADs and waveguide-integrated designs promise room-temperature performance matching or exceeding SNSPDs for quantum information and photonic computing when combined with time-gating and spatial-multiplexed detection (Na et al., 2024, Na et al., 2024).

• Simulation and Benchmarking:

Accurate, open-source simulation pipelines facilitate algorithm and system co-design, enabling the development and calibration of SPAD-specific image processing and machine learning pipelines (Suonsivu et al., 19 Jan 2026).

• Emerging Applications:

Quantum illumination, massively parallel photonic computation (Ising/Potts models), ultra-high dynamic range imaging, and event-driven visual processing all capitalize on maturing SPAD technology (Whitehead et al., 2022, Ma et al., 2020, Ingle et al., 2019).

Research continues to push SPAD performance toward physical noise limits, monolithic integration, and greater application specificity (An et al., 24 Jul 2025, Yu et al., 2024, Govdeli et al., 2023). The field is moving toward scalable, CMOS- and photonic-compatible single-photon detectors and arrays, setting the stage for transformative advances in quantum technologies, sensing, imaging, and information processing.