Single-Photon Avalanche Diode (SPAD) Arrays

• SPAD arrays are multi-pixel solid-state sensors that operate in Geiger mode to detect individual photons with picosecond timing precision.
• Advanced architectures like BSI and charge-focusing techniques enhance photon detection efficiency, reduce timing jitter (~240 ps), and enable scalable CMOS integration.
• These sensors power diverse applications such as ToF LiDAR, PET, quantum imaging, and neuromorphic sensing, offering high precision and low noise performance.

A single-photon avalanche diode (SPAD) array is a solid-state multi-pixel sensor capable of detecting individual photons, with per-pixel time resolution reaching tens to hundreds of picoseconds. SPAD arrays operate each diode pixel in the Geiger mode above breakdown, enabling single-photon sensitivity. These arrays are integral to a wide range of scientific and technological applications—ranging from time-of-flight (ToF) imaging and positron emission tomography (PET) to quantum optics, high-speed spectroscopy, and neuromorphic sensing—leveraging the unique combination of excellent timing response, statistical photon-counting, parallelism, and scalable on-chip electronics integration.

1. Device Architecture, Electric Field Design, and Fabrication

State-of-the-art SPAD arrays embody advanced device architectures to optimize photon detection efficiency (PDE), timing jitter, fill factor, and scalability. A representative example is the backside-illuminated (BSI), charge-focusing SPAD design using a customized 130 nm CMOS process (Sieleghem et al., 2022). Each pixel features:

• Absorption (Epi) region: A 10.4 μm-thick lightly doped silicon layer (N_D ≈ 1×10¹² cm⁻³) for efficient near-infrared (NIR) photon absorption.
• Multiplication region: A hemispherical n⁺ cathode (radius rₙ≈0.6 μm) at the pixel's core, surrounded by a p⁺ anode ring (inner radius 5 μm), forming a high-field, spherically symmetric multiplication zone via field-line crowding.
• Backside illumination: After standard CMOS frontside processing, the wafer is bonded to a carrier, thinned, selectively etched to the epi layer, then passivated and capped with a 100 nm SiN anti-reflection coating; a backside p⁺ contact ties to the anode potential.

The resulting electric field profile falls off as 1/r² from the cathode, ensuring drift-based charge transport over the entire depleted volume, with efficient charge funneling into the 2 μm diameter multiplication core. This architecture achieves uniform breakdown triggering probability across the full absorption region, minimizing position-dependent timing dispersion.

Fabrication steps are tailored for BSI operation, combining standard CMOS modules with custom wafer bonding, substrate removal, and ARC deposition to optimize NIR quantum efficiency. The device pitch is set to 15 μm, a scale enabling feasible megapixel arrays with monolithic integration of digital quenching/reset circuits and counters.

2. Photon Detection Efficiency, Jitter, and Noise Performance

SPAD array performance is quantified by the joint optimization of PDE, timing jitter, dark count rate (DCR), and afterpulsing:

• Photon Detection Efficiency (PDE): Defined as

$$\mathrm{PDE}(\lambda,V_e) = \eta_\mathrm{abs}(\lambda) \times P_\mathrm{avalanche}(V_e)$$

where $\eta_\mathrm{abs}(\lambda)$ is the external quantum efficiency (wavelength-dependent absorption and optical stack response), and $P_\mathrm{avalanche}(V_e)$ the breakdown probability for carriers injected into the multiplication zone. The BSI, charge-focusing design achieves PDE(905 nm) = 27% at 3.5 V excess bias, with a peak of ≈66% at 660 nm (Sieleghem et al., 2022).

• Timing Jitter: The full width at half maximum (FWHM) of the detector impulse response at 905 nm is 240 ps (V_e = 3.5 V). Jitter is dominated by transport variation across the depleted volume, as the field structure ensures drift-dominated, minimal-diffusion transport (no measurable diffusion tail). Lower epi thickness and core radius can enable σ_t < 150 ps.
• Dark Count Rate and Afterpulsing: CMOS-integrated pixels typically exhibit DCR ≤ 200 cps for low-noise HVCMOS, rising to ∼2 kcps for high-efficiency BCD pixels (both at room temperature) (Buttafava et al., 2020). Afterpulsing, dominated by carrier trapping-release phenomena, is reduced by quenching/hard reset, with probabilities decreasing from ≈15% at T_HO = 25 ns to <0.2% at T_HO = 200 ns (BCD technology).
• Fill Factor and Scalability: In the stated 15 μm pitch design, the geometric fill factor (active core area/pixel area) is inherently low (~2%) but the optical fill factor is effectively increased by the field-focusing effect and the addition of microlenses. Process and layout optimizations allow projected scaling to sub-10 μm pitches without major degradation in PDE or timing response.

Table: Summary of Key SPAD Array Metrics (BSI, Charge-Focusing Example)

Parameter	Value	Note/Condition
Pixel pitch	15 μm	CMOS BSI process
Absorption depth	10.4 μm	N_D ≈ 1×10¹² cm⁻³
Multiplication core	2 μm diameter	Field-line crowding
PDE (905 nm)	27%	V_e = 3.5 V
Jitter (FWHM)	240 ps	905 nm
DCR	~200–2000 cps	Tech/process-dependent
Fill factor (simulated)	40%	Without microlenses

3. Array Integration, Quenching, and System Integration

SPAD arrays are co-integrated with custom CMOS electronics, ensuring tight control of avalanche quenching, dead time, and digital output:

• Quenching and Reset: Each pixel interfaces with an integrated active quench/reset (QR) circuit and digital counter. The common anode and auxiliary "edge" diodes maintain a uniform electrostatic environment. Hold-off and recharge times are programmable, balancing afterpulsing suppression and pixel dead time.
• Scaling and Peripheral Electronics: The compact multiplication core (2 μm) and lack of trench isolation enable competitive fill factors and scalability. Digital readout is supported at the pixel or small-group level, with trade-offs between fill factor (favored by minimized in-pixel logic) and per-pixel functionality.
• Array Formats: Large arrays (tens of thousands to megapixels) are practical due to mature CMOS processes and BSI manufacturing. Typical SPAD arrays for image scanning microscopy use 5×5 (75 μm pitch, ~50% fill factor) layouts (Buttafava et al., 2020), but application-driven designs now reach megapixel format.
• Optical Stack: Integration with anti-reflective coatings, back-end-of-line metal reflectors (covering ~50% of each pixel), and optional backside illumination further improve NIR response (Sieleghem et al., 2022).

4. Principles and Models of Photodetection and Depth Imaging

SPAD arrays' timing and photon-counting capabilities enable fundamental studies and modeling of single-photon detection and 3D imaging:

• Photon Counting Model: Detection events per time bin are Poisson-distributed, with each SPAD recording at most one event per gate due to dead time constraints. For time-correlated single-photon counting (TCSPC), the statistics closely follow a binomial (one-first-photon-per-pulse) or Poisson process, depending on the illumination regime (Scholes et al., 2022).
• Depth Estimation Precision: Fundamental ToF depth precision $\Delta d$ scales with jitter and detected photon count:

$\Delta d = \frac{c}{2} \frac{\sigma_t}{\sqrt{N}}$

where $c$ is the speed of light, $\sigma_t$ is the timing jitter per pixel, and $N$ is the number of detected photons. With σ_t = 240 ps, Δd ≈ 3 cm; with σ_t < 150 ps, sub-2 cm is accessible.

• Numerical Simulation: Realistic data generation for SPAD-based depth imaging leverages a signal-plus-background likelihood function, dead-time effects, first-photon sampling, and Fisher Information-based analysis. Simulation pipelines follow the system's timing, pulse characteristics, optics, and detector specifics, yielding accurate performance bounds and synthetic data for a variety of conditions (Scholes et al., 2022).

5. Applications: From ToF LiDAR to Quantum Imaging and Biophotonics

SPAD arrays are at the core of several advanced imaging and sensing domains:

• Time-of-Flight (ToF) LiDAR: High PDE at 900–950 nm and sub-nanosecond timing enable dense, large-format arrays for 3D sensing with <3 cm depth resolution, robust background rejection, and scalable array deployment. Integration of timing electronics supports low-voltage, low-power operation crucial for embedded and mobile systems (Sieleghem et al., 2022).
• Quantum Imaging and Correlation: SPAD arrays facilitate measurement of higher-order photon correlations, super-resolution quantum imaging, entanglement, and photon-number-resolving detection for quantum information science. For instance, arrays with >50% peak PDE and timing jitter <150 ps support multi-photon correlation from single emitters (Lubin et al., 2019).
• Fluorescence Lifetime Imaging (FLIM) and Microscopy: Large arrays with high timing precision are used for laser-scanning microscopy and FLIM, offering spatial parallelism and time-tagged event streams. Designs with asynchronous, event-based readout and per-pixel quenching circuits achieve >60% PDE and <200 ps timing jitter, substantially improving spatial resolution and signal-to-noise (Buttafava et al., 2020, Bruschini et al., 2019).
• Neuromorphic and Ultra-Fast Imaging: Event-driven SPAD arrays with on-chip feature extraction realize low-latency, high-throughput object recognition and high-speed burst photography, leveraging the binary, timestamped photon stream for data compression and robust performance under extreme photon starvation (Afshar et al., 2019, Ma et al., 2020).

6. Challenges and Prospects: Scaling, Fill Factor, and Advanced Integration

SPAD array technologies confront several design and fabrication challenges as array formats scale and application domains broaden:

• Fill Factor vs Pixel Functionality: Trade-offs between in-pixel electronics (counters, TDCs, feature extraction circuits) and geometric fill factor remain at the technological frontier. Adoption of microlens arrays and field-focusing architectures mitigate losses due to inactive area.
• Process Compatibility and Uniformity: Integration with advanced CMOS nodes (down to 65 nm) and monolithic BSI processes allows aggressive scaling, but process-induced variabilities in breakdown voltage, dark noise, and PDE can limit yield and uniformity.
• Optical Crosstalk and Isolation: As arrays densify, mitigation of avalanche photon-induced crosstalk via deep-trench isolation, metal shielding, or active edge biasing becomes critical.
• Future Integration: 3D stacking (separate SPAD and logic tiers), backside-illumination, and embedded photonics (including direct hybridization with waveguides for quantum circuits) are active research areas for achieving higher fill factors, improved PDE, and tight integration with computational pipelines (Gualandi et al., 6 Dec 2025, Dolphin et al., 5 Sep 2025).
• Application-Driven Design: Performance requirements for ToF LiDAR, PET, microscopy, quantum information, and neuromorphic processors drive distinct engineering optimizations in pixel pitch, quench timing, counter depth, and interconnect architecture.

Ongoing research aims to combine high PDE (especially extending >40% into the NIR), sub-100 ps jitter, >50% fill factor (with microlenses or BSI), dense scaling (≤10 μm pitch), and advanced digital integration—ushering in a new era of single-photon imaging, ranging, and quantum measurement at scale (Bian et al., 2022, Gulinatti et al., 2020, Sieleghem et al., 2022).