Ultra-Low-Power Multi-core Microcontrollers

• Ultra-low-power multi-core microcontrollers are integrated systems featuring clustered RISC-V or ARM cores, specialized accelerators, and dynamic power management for edge analytics.
• They employ energy-efficient pipelines, mixed-precision SIMD units, and multi-level memory hierarchies to achieve leading energy efficiency and high computational throughput under strict power and area constraints.
• Their advanced scheduling, explicit memory tiling, and runtime adaptations enable versatile deployment in IoT, biomedical, and energy-harvesting environments.

Ultra-low-power multi-core microcontrollers are highly integrated systems optimized for sub-100 mW operation, targeting edge analytics in pervasive IoT, autonomous robotics, biomedical, and batteryless “intermittent” environments. These microcontrollers combine tightly-coupled clusters of RISC-V or ARM cores—with architectural advances for data-parallelism, mixed-precision compute, and aggressive power management—with specialized accelerators and rich memory hierarchies to achieve leading energy efficiency, high computational throughput, and flexible workload support even under severe power, area, and cost constraints.

1. Architectural Principles and Processing Clusters

Typical ultra-low-power (ULP) multi-core microcontrollers feature a two-level core hierarchy: a low-power fabric controller for system management and a compute cluster of 8–16 in-order RISC-V or (less commonly) ARM cores. Example platforms include Vega (10-core, 8+1 cluster plus manager) (Rossi et al., 2021), GAP9/GWT GAP9 (10-core or 8+ FC) (Frey et al., 2023, Crupi et al., 2024, Marchei et al., 9 Apr 2026), Shaheen (8 RV32 cluster + Linux-class RV64 host) (Valente et al., 2024), and HULK-V (8-core PMCA + RV64 host) (Valente et al., 2022).

Clusters adopt energy-efficient pipelines (4–6 stages), often enhanced with per-core SIMD datapaths, single-cycle MAC/FMA, hardware loops, and DSP/vector extensions (e.g., XPULP, Flex-V, Dustin’s flexible DOTP) (Ottavi et al., 2022). Architectures achieve fine-grain precision configurability from 2b to 32b, with mixed-precision SIMD units and bit-field steering (as in Dustin's CSR-based format register). Shared TCDM scratchpads (64–256 kB) with multi-bank single-cycle access and DMA engines enable full-bandwidth data path utilization.

Accelerators are tightly integrated: CNN engines (e.g., HWCE (Rossi et al., 2021), NE16 (Frey et al., 2023, Moosmann et al., 2023, Marchei et al., 9 Apr 2026)), CGRA and IMC blocks (Machetti et al., 2024), and microcoded ML wake-ups (Rossi et al., 2021). High-throughput (32–58 GOPS) and energy efficiency (up to 1.15 TOPS/W (Ottavi et al., 2022)) are attained in quantized workloads; hardware lockstep reduces I-fetch power by 38% in Dustin, while maintaining versatile MIMD execution.

2. Power Management: Gating, DVFS, Retention, and Intermittency

ULP multi-core microcontrollers target both always-on sensing and burst compute with aggressive multi-level power management:

• Power and clock gating: Domains for SoC, cluster, accelerators, and memory banks can be independently gated, down to µW-scale standby (e.g., Vega’s MRAM sleep, 1.7 µW (Rossi et al., 2021); X-HEEP’s bank-level gating (Machetti et al., 2024)).
• State retention: Retentive SRAM retains context for µs-scale wake-up (minimum 16 kB in Vega, leakage cost 1.2–112 µW) (Rossi et al., 2021).
• DVFS (Dynamic Voltage and Frequency Scaling): Extensive tuning, 0.6–1.2 V/32 kHz–900 MHz, lets systems “race to sleep” (Machetti et al., 2024, Valente et al., 2022). Trade-offs are modeled by

$$E_{\mathrm{op}} = \frac{P_{\mathrm{op}}}{\text{Throughput}}$$

with higher V/f improving throughput but increasing static power.

• Intermittent and energy-harvesting operation: PEARL introduces a three-threshold voltage tracker for checkpointing, with off-chip FRAM only used sparingly for backup/restore, allowing checkpoint overheads suitable for sub-mJ harvested environments (Akhunov et al., 31 Oct 2025). SRAM retention via a low-power mode (LPMRM) is sufficient at moderate harvested power, while aggressive gating and adaptation algorithms (using EWMA-predicted ambient power) switch between core configurations for minimal energy.

3. Memory Hierarchies and Accelerator Integration

Dual- or triple-level memory hierarchies are universal: multi-banked L1 TCDM/SRAM (64–256 kB), near-memory L2 SRAM (0.5–4 MB), and hybrid non-volatile NVM (MRAM or HyperRAM up to 512 MB off-chip). DMA engines provide double-buffering and low-latency data movement across all levels (Rossi et al., 2021, Valente et al., 2022, Valente et al., 2024, Frey et al., 2023, Machetti et al., 2024).

Heterogeneous accelerator integration is supported via standard or extensible interfaces (XAIF in X-HEEP (Machetti et al., 2024)), with fine-grained clock/power gating and interrupt-tied wakeup domains per accelerator (Rossi et al., 2021). Processor-like (CGRA) and memory-like (IMC) accelerators benefit from independent data paths, and key power savings (4.9×–4.8× in HEEPocrates for DNN layers (Machetti et al., 2024)) derive from offloaded computation and in-memory compute.

Non-volatile memories (MRAM in Vega (Rossi et al., 2021), FRAM in PEARL (Akhunov et al., 31 Oct 2025), HyperRAM in Shaheen/HULK-V (Valente et al., 2024, Valente et al., 2022)) enable deep sleep and extremely low boot overheads. The digital-only DRAM PHY used in HULK-V reduces area and energy by up to 10× vs. LPDDR PHYs (Valente et al., 2022).

4. Workload Distribution, Scheduling, and Parallelization

Work partitioning exploits static and dynamic analytics to map data-parallel regions across clusters. Static ML-based classifiers (decision trees trained on source code features: ALU op count, memory traffic, OpenMP parallelism) enable compile-time selection of energy-optimal core counts (C*), achieving within 5% of the minimal energy for a given OpenMP kernel 80% of the time (Parisi et al., 2020).

Runtime scheduling for data flows adheres to the following principles:

• Explicit tiling for memory hierarchy: Temporal/channel/output tiling with analytical constraint programming minimizes scratchpad usage (Burrello et al., 2022). DMA overlaps transfer/compute for both DNNs and TCN inference (Burrello et al., 2022, Frey et al., 2023, Crupi et al., 2024).
• Cluster fork/join: Parallel execution uses hardware or software barriers (e.g., PULP SDK, bioGAP round-robin FFT dispatch (Frey et al., 2023, Marchei et al., 9 Apr 2026)).
• Energy-aware scaling: PEARL’s runtime selectively activates/deactivates cores and adapts checkpointing frequency based on predicted available ambient power, thereby minimizing checkpoint overheads and maximizing throughput in energy-harvesting settings (Akhunov et al., 31 Oct 2025).
• Lockstep execution: Dustin's VLEM mode broadcasts a single instruction stream to followers (clock gating their I-fetch/caches), reducing dynamic power by 38% for compute-dominated kernels with <3% throughput loss (Ottavi et al., 2022).

5. Quantitative Performance and Efficiency Benchmarks

ULP multi-core microcontrollers achieve state-of-the-art compute and efficiency metrics in edge AI, DSP, and time-series analytics. Representative performance numbers:

Platform	Compute Cluster	Active Power	Peak Throughput	Efficiency	Sleep/Standby
Vega (Rossi et al., 2021)	8×RV32 + HWCE	49.4 mW	INT8: 32.2 GOPS (HWCE)	1.3 TOPS/W	1.7 µW (MRAM retentive)
GAP9 (Frey et al., 2023, Moosmann et al., 2023, Marchei et al., 9 Apr 2026)	8×RV32 + NE16	31–41 mW	INT8: 32.2 GMAC/s (NE16)	330 µW/GOP, 105 µJ/inf (Tinyissimo YOLO, NE16)	Deep sleep ≈45 µW
Dustin (Ottavi et al., 2022)	16×RV32 (DOTP)	50.4 mW	58 GOPS (2b)	1.15 TOPS/W	—
Shaheen (Valente et al., 2024)	8×Flex-V RV32	70 mW	90 GOp/s (2b), 7.9 GFLOP/s (FP16)	1.8 TOPS/W (2b), 150 GFLOP/s/W (FP16)	9–19 mW idle
HULK-V (Valente et al., 2022)	8×RV32 PMCA	88.2 mW	13.8 GOPS (SIMD)	157 GOPS/W	—

Actual energy per operation is in the sub-pJ range: Vega achieves $E_\mathrm{op} \approx 0.87$ pJ (Ottavi et al., 2022), GAP9’s NE16 achieves 105–150 µJ/inference (TinyissimoYOLO) at <10 ms latency (Moosmann et al., 2023), and 2.2–3.6 µJ/sample in biosignal streaming/on-device processing (Frey et al., 2023). ML inference speedups up to $22\times$ (vs. Cortex-M4F) and 69% energy reductions have been measured for real-world sensor scenarios (Wang et al., 2019).

6. Application Domains and Case Studies

ULP multi-core microcontrollers underpin end-nodes in IoT, drones, wearables, and batteryless sensors:

• Edge AI and Embedded Learning: Deployed models include DNN/CNN (Vega, TinyissimoYOLO, SSDLite-MobileNetV3), TCNs, and FFT pipelines for wearable EEG/BCI and time-series classification (Frey et al., 2023, Crupi et al., 2024, Burrello et al., 2022).
• Batteryless, energy-harvesting operation: PEARL demonstrates robust multicore operation powered by harvested RF/solar, maintaining minimal checkpoint overheads and orders-of-magnitude gains in throughput and energy per task (Akhunov et al., 31 Oct 2025).
• Sensor fusion and event-based vision: TinyDEVO achieves state-of-the-art deep event camera visual odometry (1.2 FPS, <86 mW) on GAP9, with mixed-precision quantization and deep pruning (Marchei et al., 9 Apr 2026).
• Healthcare and biomedical edge: HEEPocrates integrates CGRA/IMC accelerators with multiple RV32 cores for biosignal classifiers, maintaining energy profiles competitive with leading commercial MCUs (Machetti et al., 2024).
• Security and system-level OS coexistence: Shaheen and HULK-V integrate RV64 hosts with secure virtualization, low-cost HyperRAM, and PMCA clusters, enabling standard OS stacks (Linux) plus real-time offloads in under-250 mW (Valente et al., 2024, Valente et al., 2022).

7. Design Trade-Offs, Best Practices, and Outlook

Designs emphasize:

• Hierarchical clock/power gating and rapid wake-up (event-unit hardware resume in 2 cycles (Rossi et al., 2021))
• Maximizing scratchpad utilization via explicit tiling/partitioning, minimizing off-cluster memory traffic (Burrello et al., 2022, Ottavi et al., 2022, Moosmann et al., 2023)
• Aggressive exploitation of mixed-precision, SIMD/MAC, and hardware scheduling for close-to-accelerator performance without sacrificing programmability (Ottavi et al., 2022, Marchei et al., 9 Apr 2026)
• Compiler and software stack advances: feature-driven static energy minimization (Parisi et al., 2020), automated kernel-to-cluster mapping (Burrello et al., 2022), and open-source toolkits for Rust and IREE–enabled multicore TinyML (Huang et al., 10 Dec 2025).
• Modular accelerator integration via open interfaces (XAIF) (Machetti et al., 2024)
• Field upgradability and scalable OTA updates as memory hierarchies become more multi-tiered and code/data footprints grow (Huang et al., 10 Dec 2025)

Adoption of digital-only DRAM PHYs and off-chip HyperRAM/MRAM (vs. LPDDR) reduces system energy and area at limited bandwidth penalty. Heterogeneous architectures coupling high-performance Linux-class cores with parallel PMCA clusters enable execution of both complex OS software and real-time/RTOS workloads (Valente et al., 2022, Valente et al., 2024).

Power-constrained workload selection, dynamic adaptation, and energy-aware partitioning are critical for operation at the edge of energy limits (e.g., batteryless and deeply embedded devices), as is demonstrated by the analytical execution models and runtime adaptation strategies of PEARL (Akhunov et al., 31 Oct 2025).

In summary, ULP multi-core microcontrollers represent the current frontier in edge computation under tight energy, area, and thermal constraints, matching (and in some cases exceeding) dedicated accelerator efficiency for a broad range of sensor-driven, AI-enabled, and real-time analytics workloads.