Xilinx Zynq UltraScale+ MPSoC Overview

Updated 1 December 2025

Xilinx Zynq UltraScale+ MPSoC is a heterogeneous system-on-chip that integrates high-performance ARM processors with large-scale FPGA fabric for versatile real-time applications.
The platform enables efficient hardware/software partitioning, supporting advanced workloads like computer vision, neural network acceleration, and secure trusted execution.
Its flexible design supports scalable hardware accelerators and optimized resource utilization, making it ideal for both industrial deployments and cutting-edge academic research.

The Xilinx Zynq UltraScale+ MPSoC is a heterogeneous system-on-chip (SoC) that tightly integrates a high-performance ARM-based processing system (PS) with a large-scale programmable logic (PL) fabric derived from Xilinx’s UltraScale+ FPGA architecture. This class of devices enables fine-grained hardware/software partitioning, enabling the deployment of complex, real-time digital systems in domains ranging from computer vision and neural network acceleration to embedded trust management and event-driven computation. The Zynq UltraScale+ MPSoC is a key platform for both industrial deployments and cutting-edge academic research, offering a feature set that combines substantial on-chip resources, rich I/O capabilities, and highly configurable computational pipelines.

1. Architectural Overview

The Zynq UltraScale+ MPSoC combines several major subsystems:

Processing System (PS): Quad-core ARM Cortex-A53 application processors, dual-core ARM Cortex-R5 real-time processors, integrated L2 cache, DDR4/LPDDR4 memory controller, and a suite of on-chip peripherals (Ethernet, USB, SDIO, I²C, SPI, UART, GPIO, timers). The PS operates under Linux or real-time operating systems and manages control, pre/post-processing, and general-purpose computing tasks (Wasala et al., 2022, Li et al., 30 Dec 2024).
Programmable Logic (PL): UltraScale+-derived FPGA fabric, featuring a large number of lookup tables (LUTs), flip-flops (FFs), distributed RAM, block RAM (BRAM, 36 Kb), ultra RAM (URAM, 288 Kb), and DSP48E2 slices (multiply-accumulate units). High-bandwidth AXI interconnects, ACE/HP/GP AXI bus support, and DMA engines are exposed for high-throughput PS-PL communication.
Memory and Interconnect: Up to 16 GB of DDR4 (PS-side), on-chip OCM (256 KB), robust AXI-based interconnect for both control and data pathways; external high-speed interfaces for PCIe, MIPI-CSI, and multi-Gbps transceivers (GTH/GTY).
Security and System Management: Built-in support for ARM TrustZone, integrated cryptographic engines (AES-GCM, SHA3-384, RSA), secure boot via Configuration Security Unit (CSU), eFuse/BBRAM key management, and processor-controlled (CSUDMA) partial reconfiguration (Wang et al., 2023, Mao et al., 18 May 2025).

This heterogeneous integration allows deterministic, real-time interoperability between tightly-coupled software and hardware pipelines, prime for high-throughput, low-latency embedded applications.

2. Application Domains and Typical Use Cases

The Zynq UltraScale+ MPSoC is leveraged across multiple domains:

High-Throughput Computer Vision: Real-time HOG+SVM pedestrian detection at 4K resolution (3840×2160, 60 fps) is achieved by mapping the HOG feature extractor and SVM scoring to PL, with bounding-box overlay and non-maximum suppression on the PS. This enables 600 million pixels/sec throughput and <10 W power consumption (Wasala et al., 2022). Connected-component labeling for UHD video at 4 ppc and 60 fps is also realised with minimal (<1%) fabric resource usage and deterministic latency (Kowalczyk et al., 2021).
Neural Network Acceleration: INT8 quantized DPU inference via Xilinx Vitis AI achieves up to 2.46 TOPS and 1,021 FPS on CIFAR-10, with energy efficiency improvements of up to 6.3× over CPU baselines (Li et al., 30 Dec 2024). Custom hardware accelerators for power-of-two quantized convolution (BAC vs MAC) demonstrate up to 1.42× energy efficiency and 29% dynamic power reduction; up to 50% zero-weight skipping is supported for further energy gains (Przewlocka-Rus et al., 2022). XNOR (binary) CNNs for traffic sign classification reach ~580 FPS at 96% accuracy with the FINN toolflow (Przewlocka-Rus et al., 2021).
Scientific and Industrial Instrumentation: BPM systems for high-energy accelerators incorporate Zynq UltraScale+ for sub-μm positional accuracy and sub-degree phase stability in multi-channel (4 × 250 MSPS) data acquisition, using integrated JESD204B RX, digital down-conversion, time-tagging, and thermal/phase drift compensation (Liu et al., 18 Sep 2025).
Streaming Event Processing and Edge AI: Ultra-low-latency event-based vision solutions (e.g., HOMI platform) leverage Zynq UltraScale+ for integrated MIPI-CSI RX, histogram and time-surfaces in hardware, and custom sparse-CNN inference, achieving 1,000 fps, <1.15 ms latency, and <2 W dynamic power (H et al., 18 Aug 2025).
Trusted Execution Environment (TEE): Multiple works establish OP-TEE/TrustZone based secure architectures with hardware-anchored (SRAM/RO-PUF) attestation, runtime reconfiguration, and TPM/vTPM support for end-to-end IP core measurement, deployment, and invocation with formal security guarantees (Wang et al., 2023, Mao et al., 18 May 2025).
Custom IOMMU/SMMU Use: Full ARM SMMU support for integrating virtual address spaces across PS and PL DMA masters, allowing non-coherent or coherent memory exposure to hardware accelerators under Linux, with dynamic page-map and TLB support (Psistakis, 24 Nov 2025).

3. Hardware Accelerator Design Paradigms

A key attribute of the Zynq UltraScale+ MPSoC is the capacity for direct mapping of algorithmic computational kernels into deeply pipelined, vectorized hardware engines:

Matrix Multiplication Overlays: BISMO overlays employ a bit-serial, LUT- and compressor-based architecture targeting binary/few-bit precision workloads, scalable to 15.4 TOPS (Ultra96, ZU3EG) at 2.13 TOPS/W. No DSP usage is required for binary matrix-matrix multiply, which is scheduled over resource-tunable DPU arrays, with precision-flexible interfaces (Umuroglu et al., 2019).
Sparse Neural Networks and Data-Dependent Skipping: In-house accelerators (e.g., RAMAN) and BAC-based PEs leverage runtime activation/weight sparsity for skipping unnecessary MACs, clock gating, and lane selection. Pruning and dynamic zero-skipping logic maintain high pipeline utilization and performance for structured or unstructured sparse NNs (Przewlocka-Rus et al., 2022, H et al., 18 Aug 2025).
High-Speed Streaming Pipelines: Fixed-function pre-processing elements (gradient pipelines, histogram accumulators, time-surface generators, event filters) and control-oriented FSMs ensure the high-throughput streaming of input data; e.g., 4 ppc/150 MHz for HOG+SVM (Wasala et al., 2022), 387 MHz for event-based IIR filtering (385.8 MEPS) (Kowalczyk et al., 2022).
Resource and Memory Optimization: Wide vector lanes (4–8 ppc), packed BRAM/URAM usage, ping-pong buffer schemes for double-buffering, distributed RAM for fast-access state, and overlapping fetch/execute/result pipelines maximize parallelism and data reuse.

4. Performance Characteristics and Resource Utilization

Quantitative results across deployments highlight the practical impact of the Zynq UltraScale+ MPSoC architecture:

Application Domain	Throughput/Latency	Resource Utilization (PL)	Power (Total/PL)
HOG+SVM detection	4K@60fps, 600 Mpixels/s, ~260 µs latency	46% LUT, 49% FF, 32% DSP, 3.4% BRAM, 1.7% URAM	9.6 W (total), Δ=4.3 W
Vitis AI (CNN, DPU)	1,021 FPS, 2.46 TOPS (2×B4096 cores)	45.9% LUT, 67.3% FF, 43.1% DSP, 82.2% BRAM	17.02 FPS/W (2-thread)
BAC vs. MAC (NN Conv)	350 GOPS at 350 MHz	20% fewer LUTs, 9% fewer FFs (vs MAC)	0.214 W (BAC, 512 PE)
PointNet (LiDAR)	182–280 GOPS, 19.8–34.6 ms/frame	8–13% LUT/FF, 60% DSP, 37–50% BRAM/URAM	Not specified
EventAI (HOMI)	1,000 fps (Net16), <1.15 ms total latency	33% LUT, 10% FF, 31% BRAM, <1% DSP	<5 W (total board)
Binary CNN (FINN)	582 FPS, ~1.7 ms latency, 96.2% acc.	6.14% LUT, 4.62% FF, 22.1% BRAM, 0% DSP	3.547 W

This table reflects measured resource figures only where explicitly reported in the corresponding studies (Wasala et al., 2022, Przewlocka-Rus et al., 2021, Li et al., 30 Dec 2024, Przewlocka-Rus et al., 2022, H et al., 18 Aug 2025, Bai et al., 2020, Kowalczyk et al., 2022).

5. Security, Trusted Computing, and Embedded TEE

Zynq UltraScale+ MPSoC devices integrate several primitive building blocks for trusted computation:

Trusted Boot and Chain-of-Trust: The CSU manages cryptographic measurement and verification of all boot stages via SHA3-384, enforcing integrity via eFuse/BBRAM-programmed root keys. Boot measurements are chained in dedicated PCR registers (as defined in TPM 2.0), ensuring attestation (Wang et al., 2023, Mao et al., 18 May 2025).
OP-TEE and TrustZone: The ARM TrustZone extension separates secure (TEE) and non-secure (REE) worlds. Secure interconnects use AXI AWPROT/ARPROT attribute bits to gate off sensitive peripherals (e.g., PCAP, PL-PUF) from non-secure masters. Only TEE software is permitted to trigger runtime reconfiguration or invoke secure IP deployments (Wang et al., 2023, Mao et al., 18 May 2025).
TPM/vTPM Integration: Hardware and software vTPMs support TPM 2.0 command handling, secure key storage, session-key negotiation (AES-GCM), dynamic PCR extension, and remote attestation. Security guarantees are anchored in SRAM-PUF or RO-PUF modules and enforced by cryptographic challenge-response protocols (Mao et al., 18 May 2025).
Formal Security Properties: Protocols enforce mutual authentication, non-repudiation, and confidentiality between user, TEE, and vTPM, protecting against KPA, MITM, rollback, and FPGA reconfiguration attacks.

6. System Integration, I/O, and Network Capabilities

The device family offers a rich set of integration options:

I/O Bandwidth and Memory Hierarchy: AXI4-HP and AXI4-Stream channels supply multi-Gigabit/s streaming from DDR4 to PL. DMA engines and page-table-based ARM SMMU allow both the PS and hardware accelerators in the PL to access (and translate) virtual address spaces, including advanced modes exposing Linux user-space buffers to PL DMA (Psistakis, 24 Nov 2025).
Precision Timing and Synchronization: The platform supports deterministic clocking (JESD204B multi-lane sync, White Rabbit for sub-ns time-tagging, PLL/LMK04832-based phase alignment), crucial for data-acquisition and accelerator instrumentation (Liu et al., 18 Sep 2025).
Network and External Interfaces: Direct support for high-speed transceivers (up to 16 Gb/s), uTCA.4 AMC form factor for modular systems, as well as MIPI-CSI, SGMII for 1/10 GbE, and MLVDS-triggered event-log delivery.
Thermal and Power Management: On-board sensors and firmware-driven thermal management schemes support automated calibration against phase drift and thermal run-away. Power consumption for event processing, CNN inference, and real-time vision pipelines typically remains within a few watts due to fine-grained hardware specialization (Liu et al., 18 Sep 2025, H et al., 18 Aug 2025, Przewlocka-Rus et al., 2022).

7. Design Principles, Trade-Offs, and Future Directions

Design studies consistently highlight principles and trade-offs:

Hardware/Software Partitioning: Maximal offload of compute-intensive kernels to pipelined, vectorized hardware in PL, with the PS managing orchestration, control, and sequential logic (Wasala et al., 2022, Li et al., 30 Dec 2024, Bai et al., 2020).
Vectorization and Pipeline Parallelism: Optimal throughput is achieved through architecture choices such as 4–8 pixel-per-clock datapaths, parallel MAC lanes, ping-pong buffering, and careful placement of line/histogram buffers in BRAM/URAM (Kowalczyk et al., 2021, Kowalczyk et al., 2022).
Approximate and Low-Precision Arithmetic: Hardware-okay approximation in core functions (e.g., square-root, orientation assignment in HOG), bit-serial computation for matrix multiply (BISMO), and quantized (even binary) NNs yield substantial resource and power savings with marginal accuracy degradation (Umuroglu et al., 2019, Przewlocka-Rus et al., 2022, Przewlocka-Rus et al., 2021).
Reuse and Scalability: Parameterized generator flows enable scaling of computational overlays (e.g., DPU/BISMO arrays) to fit device or application resource budgets. Designs can be extended to higher data rates, larger image resolutions, or deeper NNs without fundamental pipeline redesign (Umuroglu et al., 2019, Li et al., 30 Dec 2024).
Security and Attestation: End-to-end integrity tracking, secure deployment and invocation of hardware IPs, and mutual attestation mechanisms are now routinely co-designed with functional accelerators in cloud and edge deployments (Mao et al., 18 May 2025, Wang et al., 2023).
Future Scalability: Leveraging newer HBM-enabled UltraScale+ variants is suggested for even higher bandwidth or multi-scale vision pipelines, as well as for scaling up parallel accelerators or multi-task inference on single chip (Wasala et al., 2022, Li et al., 30 Dec 2024, H et al., 18 Aug 2025).

A plausible implication is that ongoing advances in integrating high-bandwidth memory, further scaling programmable logic, and improving PS-PL coherency will extend the domain of real-time, heterogeneous SoC systems to computational workloads that previously required dedicated GPU, ASIC, or cluster-based solutions.

References:

(Wasala et al., 2022, Li et al., 30 Dec 2024, Przewlocka-Rus et al., 2022, Bai et al., 2020, Przewlocka-Rus et al., 2021, Kowalczyk et al., 2021, Mao et al., 18 May 2025, Wang et al., 2023, H et al., 18 Aug 2025, Kowalczyk et al., 2022, Liu et al., 18 Sep 2025, Psistakis, 24 Nov 2025)