GAP9 Microcontroller Overview

Updated 11 July 2025

GAP9 microcontroller is a RISC-V–based ultra-low-power SoC featuring a 1+9 core architecture and a dedicated neural accelerator for advanced DSP and machine learning.
It supports transprecision computing and dynamic voltage/frequency scaling to optimize energy efficiency in IoT, wearable, and embedded vision applications.
Its versatile sensor interfacing and secure firmware testing methods enable real-time edge processing in diverse intelligent, low-energy systems.

The GAP9 microcontroller is a parallel, RISC-V–based, ultra-low-power system-on-chip (SoC) produced by GreenWaves Technologies. It is specifically engineered for high-efficiency digital signal processing (DSP) and ML at the edge, accommodating the stringent power, form factor, and real-time computation requirements of modern IoT, wearable, and embedded vision applications. GAP9’s architecture, multispectral hardware acceleration, and integration with a wide array of sensor and wireless components have led to its deployment in domains ranging from biosignal acquisition to drone navigation and real-time computer vision.

1. Architectural Overview and Technical Features

GAP9 is built around a heterogeneous multi-core architecture comprising one Host RISC-V core and a compute cluster of nine additional RISC-V cores, complemented by hardware neural network acceleration (NE16) and a versatile memory subsystem. Key architectural elements include:

Parallel Compute Cluster: 9 RISC-V cores (in a 1+9 configuration) operate in parallel at frequencies up to 370 MHz (Frey et al., 2023, Frey et al., 12 Jun 2024, Müller et al., 27 Jun 2024, Bompani et al., 28 Aug 2024), achieving peak throughputs of $150\,\mathrm{GOPS}$ for integer workloads, $15.6\,\mathrm{GOP/s}$ for DSP tasks, and $32.2\,\mathrm{GMAC/s}$ for ML inferences (Müller et al., 27 Jun 2024).
Transprecision Support: Full support for IEEE 32-bit, 16-bit, and bfloat16 floating-point formats, enabling fine-grained trade-offs between precision and energy use (Müller et al., 27 Jun 2024).
NE16 Neural Accelerator: A dedicated hardware block streamlining 16- and 8-bit convolutions, achieving up to $\sim$ 10.9 MAC/cycle and delivering 7.2× inference acceleration over software-only RISC-V cores (Bompani et al., 28 Aug 2024).
Energy Optimizations: Dynamic voltage and frequency scaling, automatic clock gating, and deep sleep (as low as $45~\mu$ W) allow highly granular adjustment of power consumption to task requirements (Frey et al., 2023, Frey et al., 12 Jun 2024).
Memory Hierarchy: On-chip L1 scratchpad (e.g., $128~\mathrm{kB}$ ) and a larger L2 memory (e.g., $1.5~\mathrm{MB}$ ) support low-latency access patterns; external PSRAM and flash are used for weight/code storage.

The processor is closely coupled to high-speed sensor and wireless interfaces (SPI, I $^2$ C, UART, Bluetooth, WiFi), facilitating direct acquisition, processing, and feature extraction from multimodal input sources.

2. Edge Processing for Biosignal and Wearable Applications

GAP9 is a central computational resource in platforms such as BioGAP and GAPSES smart glasses, where it executes real-time DSP and ML inference on physiological signals—enabling energy-efficient, high-privacy wearable biosignal processing (Frey et al., 2023, Frey et al., 12 Jun 2024).

DSP/FFT Acceleration: GAP9 performs parallelized FFT and other DSP operations with energy per sample as low as $2.2\,\mu$ J in onboard processing mode; $\sim$ 16.7 Mflops/s/mW energy efficiency is reported for floating-point FFTs (Frey et al., 2023).
ML on the Edge: NE16 hardware enables efficient inference of convolutional and recurrent neural networks, allowing features or decisions (e.g., for BCI, biometric ID, or eye movement recognition) to be computed locally without streaming raw data (Frey et al., 2023, Frey et al., 12 Jun 2024).
Power and Lifetime: Full wearable systems (including analog frontend, GAP9, BLE module, and battery management) achieve operations within 16–26 mW (e.g., $18.2~\mathrm{mW}$ for BioGAP, $16.28~\mathrm{mW}$ for GAPSES) with per-inference energy as low as $24\,\mu$ J (EOG) and $121\,\mu$ J (EEG), supporting multi-hour to all-day usage with a $75~\mathrm{mAh}$ battery (Frey et al., 2023, Frey et al., 12 Jun 2024).

Technical Example:

For N-class EOG classification, the real-time information transfer rate (ITR) is computed as: $ITR = \frac{60}{T}\left( \log_{2} M + P \log_{2} P + (1-P)\log_{2}\left(\frac{1 - P}{M-1}\right) \right)$ where $M$ is the number of classes, $P$ the accuracy, and $T$ the window length in seconds (Frey et al., 12 Jun 2024).

3. On-device Vision and AI in Mobile and Autonomous Platforms

GAP9’s high-throughput ML acceleration and energy efficiency have led to its adoption in resource-constrained vision systems, notably in nano-drone navigation and low-power sensor nodes (Müller et al., 27 Jun 2024, Bompani et al., 28 Aug 2024, Boyle et al., 22 Oct 2024).

Nano-drones (GAP9Shield): Enables real-time object detection (e.g., YOLO variants at 17 ms/inference), semantic localization, and SLAM under $100~\mathrm{mW}$ power—outperforming alternatives by 20% in RGB sample rate and enabling on-board environment modeling (Müller et al., 27 Jun 2024).
Image-based Pest Detection: For MobileNetV3-SSDLite on 320 $\times$ 240 images, the NE16 accelerator processes images in 147 ms—9.5× faster than previous MCUs (GAP8) and with only $4.85~\mathrm{mJ}$ per inference, permitting remote operation for up to 199 days on a $1000~\mathrm{mAh}$ battery (Bompani et al., 28 Aug 2024).
Efficient Small Object Detection: The DSORT-MCU approach leverages GAP9's NE16 for tiled, adaptive small object detection, obtaining F1-scores up to 95% with per-inference energy as low as $31~\mu$ J and latency 0.6–16.2 ms (Boyle et al., 22 Oct 2024).

Performance Metrics Table:

Application	Model / Task	Inference Speed	Energy	F1-Score / Accuracy
Pest Detection	MobileNetV3-SSDLite	147 ms (320×240 image)	4.85 mJ	83% (near), 72% (far)
Nano-drone Object Detection	YOLO variant	17 ms	1.59 mJ	n.a. (see task refs)
GAPSES Eye Movement	EPIDENET (EOG)	N/A	24 μJ/inference	96.68% (11 classes)
GAPSES Biometric ID	BrainMetrics (EEG)	N/A	121 μJ/inference	98.87%/99.86% (sens/spec)

4. Energy Optimization and Adaptive Computation

GAP9’s energy management is central to its suitability for edge deployments:

Dynamic Voltage/Frequency Scaling (DVFS): Allows fine modulation of compute intensity, reducing draw for light workloads and boosting performance when required.
Hierarchical Power Domains: Compute cluster, Host, and accelerators may be independently clock-gated or deep-slept as needed.
On-chip and Off-chip Memory Partitioning: DORY and Quantlab tools optimize NN model placement between L1/L2 and external memories (Frey et al., 12 Jun 2024), minimizing data movement and further reducing energy per inference.

These capabilities are reflected in long battery life projections (e.g., 12–15 hours continuous wearable operation, 199 days in imaging remote sensors) even under computationally demanding loads (Frey et al., 2023, Frey et al., 12 Jun 2024, Bompani et al., 28 Aug 2024).

5. Comparison With State-of-the-Art and Deployment Context

Studies directly compared GAP9 to previous generations (notably GAP8) and to other embedded/IoT MCU platforms (Bompani et al., 28 Aug 2024, Müller et al., 27 Jun 2024, Boyle et al., 22 Oct 2024):

Inference Acceleration: NE16 delivers up to 9.5× speedup for CNNs and 1.47× for classical algorithms over GAP8.
Energy Efficiency: Reductions up to 15× in system-level power consumption for similar workloads.
Throughput and Latency: Outperforms single-core AI decks in drones by 20% in frame rate and reduces data transmission by 97% in wearables, all with significant form factor and mass reductions.

This combination enables not only new classes of applications (onboard SLAM, real-time multi-modal biosignal fusion, pervasive object detection) but also substantial improvements in operational longevity, privacy, and deployment autonomy.

6. Security, Fuzzing, and Testing Methodologies

Firmware security and robustness are relevant in the context of microcontroller-centric platforms like GAP9. Hardware-in-the-loop fuzzing, as exemplified by the $\mu$ AFL methodology, offers a pathway for systematic defect discovery in MCU firmware (Li et al., 2022):

Non-intrusive Feedback-driven Fuzzing: Utilizes HW trace (e.g., ARM ETM, DWT features) to collect execution traces with minimal overhead and maps these to AFL-compatible coverage feedback (e.g., via dynamic basic blocks and specialized hash mapping algorithms).
Hardware-in-the-loop Execution: Directly exercises physical MCUs using debug dongles and protocol bridges, enabling accurate fuzzing of code paths (e.g., peripheral drivers) that are not faithfully modeled in rehosting/emulation.
GAP9 Adaptations: Provided similar trace infrastructure exists (or is adapted), $\mu$ AFL-like approaches can be adopted for GAP9 firmware to test both hardware- and software-adjacent code without requiring instrumented or source-level changes (Li et al., 2022).
Testing Strategies: Modular fuzzing managers, hybrid HITL and emulation, and automated test harness generation are prospective enhancements for GAP9 firmware reliability and vulnerability discovery.

7. Research Directions and Implications

Recent literature suggests the following implications and areas for future research:

Architecture-specific Toolchains: The necessity for optimized deployment workflows (e.g., DORY, Quantlab) to fully exploit GAP9’s compute/memory hierarchy (Frey et al., 12 Jun 2024).
Sensor Fusion and ML Applications: Increasing sophistication in multi-modal fusion (EEG, PPG, EOG, vision) will benefit from GAP9’s parallel and accelerator-rich architecture (Frey et al., 2023, Frey et al., 12 Jun 2024).
Expanded Security Analysis: The potential for cross-vendor fuzzing and the adaptation of grey-box fuzzers to RISC-V/GAP9 architectures is indicated (Li et al., 2022).
Adaptive Computation: Research into workload-conditional power/performance scaling and further automation of memory mapping will extend device autonomy even under expanding application complexity (Müller et al., 27 Jun 2024, Bompani et al., 28 Aug 2024).

A plausible implication is that the GAP9’s combination of high energy efficiency, flexible workload support, and secure testing pathways lays the groundwork for rapidly deployable, privacy-preserving edge intelligence in distributed sensing and automation.

In summary, the GAP9 microcontroller exemplifies current trends in ultra-low-power embedded processing by integrating a heterogeneous RISC-V compute cluster, hardware-accelerated ML capabilities, and advanced power management within a form factor and system context tailored for next-generation IoT, wearable, vision, and security-critical applications (Frey et al., 2023, Frey et al., 12 Jun 2024, Müller et al., 27 Jun 2024, Bompani et al., 28 Aug 2024, Boyle et al., 22 Oct 2024, Li et al., 2022). Its documented performance and efficiency metrics across real-world academic and commercial prototypes demonstrate its prominence as a platform for on-device intelligent processing and secure, long-term deployment at the edge.