SynCircuit: Automated RTL Circuit Generation

• SynCircuit is a framework that automatically generates new, realistic RTL circuits in HDL using a diffusion-based model combined with MCTS for redundancy optimization.
• It employs a three-phase pipeline—graph generation, constraint enforcement, and MCTS refinement—to produce circuits that meet synthesis and timing constraints.
• Augmenting training datasets with SynCircuit-generated circuits improves ML performance on PPA prediction, reducing error metrics significantly compared to baselines.

Searching arXiv for the specified paper and closely related work to ground the article. SynCircuit is a complete framework for automatically generating new, large, realistic RTL circuits in HDL format—not just variants of existing designs, but entirely new circuits with valid functionality and realistic implementation properties. It is motivated by the data bottleneck in AI for IC design and combines three major technical components: a diffusion-based generative model for directed cyclic circuit graphs, a constraint-enforcing probability-guided refinement step, and an MCTS-based optimization procedure to remove logic redundancy. The framework operates at the RTL level, outputs a synthetic circuit graph $G^{opt}$ and a corresponding HDL implementation, and is intended for use as training and benchmark data in downstream ML/EDA tasks (Liu et al., 26 Aug 2025).

1. Problem setting and formal representation

Modern AI-assisted IC design requires large-scale circuit datasets for tasks such as RTL-level PPA prediction, logic synthesis and optimization, placement/routing, congestion and timing prediction, design quality and code-style assessment, and high-level synthesis and architecture exploration. Publicly available RTL or netlist datasets are described as small and fragmented, while industrial designs are proprietary. SynCircuit addresses this by automatically generating an unlimited number of synthetic RTL circuits that have valid HDL implementations and pass synthesis, resemble real designs structurally and timing-wise, and can be used as training and benchmark data for downstream ML/EDA tasks (Liu et al., 26 Aug 2025).

The framework represents an HDL design $D$ as a directed cyclic graph through a bijective parser

$f: D \leftrightarrow G, \qquad G=(V,E,X),$

where $V$ is a set of nodes, $E$ is a set of directed edges, and $X$ contains node attributes. Nodes represent basic RTL objects including IO ports, arithmetic and logic operators, registers, bit selection, and concatenation operators. Edges represent directed signal flow, and node attributes include type and output width.

A central design choice is the use of directed cyclic graphs rather than DAGs. At the RTL graph level, sequential circuits contain cycles that traverse registers; such cycles are legal and necessary. Only combinational loops, defined as cycles that do not include any register nodes, are illegal. Validity is therefore expressed through circuit constraints $\mathcal{C}$, with two core components: fan-in correctness for every node type and absence of combinational loops. The fan-in condition is written as

$$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$

and a valid graph satisfies $\mathcal{C}(G)=0$.

2. Diffusion model for directed cyclic circuit graphs

SynCircuit formulates RTL generation as a three-phase pipeline: $P(G)\;\overset{\circled{1}}{\longrightarrow}\;G^{ini}\;\overset{\circled{2}}{\longrightarrow}\;G^{val}\;\overset{\circled{3}}{\longrightarrow}\;G^{opt}.$

Phase	Mechanism	Output
1	DCG generation via diffusion	$D$0, $D$1
2	Probability-guided graph post-processing	$D$2
3	Logic redundancy optimization via MCTS	$D$3

In Phase 1, real HDL designs are parsed into graph form, and a diffusion-based generative model conditioned on node attributes $D$4 and node count $D$5 learns $D$6. The forward noising process acts on the adjacency matrix: $D$7 while the reverse process approximates

$D$8

Generation starts from random noisy adjacency $D$9 and iteratively denoises to obtain $f: D \leftrightarrow G, \qquad G=(V,E,X),$0 and an edge probability matrix $f: D \leftrightarrow G, \qquad G=(V,E,X),$1.

The encoder is a directed MPNN tailored for large graphs with linear complexity in $f: D \leftrightarrow G, \qquad G=(V,E,X),$2. At MPNN layer $f: D \leftrightarrow G, \qquad G=(V,E,X),$3, node embeddings are updated by directed message passing from parent nodes: $f: D \leftrightarrow G, \qquad G=(V,E,X),$4 The decoder uses a TransE-style relation embedding to model asymmetric edge directionality: $f: D \leftrightarrow G, \qquad G=(V,E,X),$5 This construction is designed specifically for large directed cyclic graphs, where asymmetric edge modeling is essential and a global topological ordering does not exist (Liu et al., 26 Aug 2025).

3. Constraint enforcement and redundancy optimization

The raw diffusion output $f: D \leftrightarrow G, \qquad G=(V,E,X),$6 often violates circuit constraints, especially fan-in rules and combinational-loop legality. SynCircuit therefore applies a sequential, probability-guided refinement procedure. For each node, the method checks whether the parent edges in $f: D \leftrightarrow G, \qquad G=(V,E,X),$7 already satisfy the constraints. If not, candidate parents are listed in descending order of $f: D \leftrightarrow G, \qquad G=(V,E,X),$8, and edges are added only if they do not create a combinational loop. The loop check asks whether there exists a path from the child back to the candidate parent in the current graph excluding register nodes. This refinement continues until each node has the required number of parents, yielding a graph $f: D \leftrightarrow G, \qquad G=(V,E,X),$9 with $V$0 (Liu et al., 26 Aug 2025).

Validity alone is not sufficient, because $V$1 may still contain heavy logic redundancy. SynCircuit therefore introduces a third phase based on Monte Carlo Tree Search over local register cones. The driving cone for a register is defined by reverse BFS from that register until hitting constant nodes, input ports, or other register nodes. Search is performed cone-by-cone to reduce complexity.

The optimization target is realism after synthesis. SynCircuit defines the Sequential Cell Preservation Ratio as the number of sequential cells in the synthesized netlist divided by the total bits in sequential signals in RTL. Real designs are reported to have SCPR typically 70–100%, while some synthetic $V$2 instances can have SCPR below 10%. The reward used during MCTS is Post-Synthesis Circuit Size,

$V$3

where larger PCS indicates that fewer nodes are removed by synthesis and hence that redundancy is lower.

States in the search tree are candidate circuit adjacencies, and actions are parent-swapping rewires that keep the total number of edges constant while preserving in-degree and out-degree. Selection and expansion use a UCB1 policy,

$V$4

The reported outcome is that, without optimization, some synthetic circuits have SCPR below 20%, whereas with MCTS optimization SCPR often exceeds 50%, approaching the real-design range.

4. HDL reconstruction, validity, and realism

Once $V$5 is obtained, the inverse parser $V$6 converts the graph back to HDL. Node types and connectivity are mapped to RTL constructs such as port declarations, arithmetic expressions, sequential logic, bit-select operations, and concatenation patterns. The resulting HDL follows realistic coding patterns, respects fan-in and type constraints, and can be synthesized with standard tools. The paper reports successful synthesis of SynCircuit-generated HDL outputs into netlists and layouts, and uses this as evidence of functional validity (Liu et al., 26 Aug 2025).

SynCircuit evaluates realism along structural, logic-redundancy, timing, and validity axes. Structural similarity is measured using 1-Wasserstein distance $V$7 on out-degree distribution, clustering coefficient, and 4-node orbit counts, together with scalar statistics such as triangle count, $V$8, and $V$9. Across the “TinyRocket” and “Core” datasets, SynCircuit with diffusion achieves best or near-best $E$0 for out-degree and clustering, and a very low orbit $E$1 of 0.344 versus values greater than 0.9 for baselines. The ablation “SynCircuit w/o diff” is described as much worse, indicating that the diffusion model is crucial for realistic structure.

Timing realism is assessed with Synopsys DC and Nangate 45nm using Worst Negative Slack and TNS/NVP. GraphRNN- and DVAE-generated circuits are reported to have unrealistically small WNS and TNS/NVP, whereas SynCircuit-generated circuits exhibit timing distributions much closer to real designs. Validity is defined not only by structural legality but also by successful synthesis and realistic post-synthesis characteristics such as SCPR and timing.

A recurring misconception is that a generative model for graphs is sufficient by itself. SynCircuit’s own ablations argue against this: the diffusion model, constraint repair, and MCTS optimization serve distinct purposes, and structural plausibility alone does not ensure EDA-valid behavior.

5. Downstream ML/EDA impact

The reported downstream study focuses on RTL-level PPA prediction. A real-design dataset of 22 designs is constructed from ITC’99, OpenCores, and Chipyard, with labels from Synopsys DC including area, register-level slack, binned WNS, and TNS. One split uses 15 designs for training and 7 for testing. The comparison includes a baseline trained only on real designs and augmented versions using 25 synthetic circuits from GraphRNN, DVAE, SynCircuit without optimization, and SynCircuit with optimization (Liu et al., 26 Aug 2025).

With 15 real designs as the base training set, the baseline achieves register-slack $E$2, MAPE $E$3, RRSE $E$4; WNS $E$5, MAPE $E$6; TNS $E$7, MAPE $E$8; and area $E$9, MAPE $X$0, RRSE $X$1. Augmenting with GraphRNN or DVAE generally does not improve performance and often worsens it. By contrast, SynCircuit with optimization yields register-slack $X$2, MAPE $X$3, RRSE $X$4; WNS $X$5, MAPE $X$6, RRSE $X$7; TNS $X$8, MAPE $X$9, RRSE $\mathcal{C}$0; and area $\mathcal{C}$1, MAPE $\mathcal{C}$2, RRSE $\mathcal{C}$3. The paper summarizes these changes as an approximately 40% relative reduction in slack MAPE and an approximately 17% relative reduction in area MAPE.

With only 5 real designs as the base training set, the baseline is substantially weaker: register-slack $\mathcal{C}$4, MAPE $\mathcal{C}$5; area $\mathcal{C}$6, MAPE $\mathcal{C}$7, RRSE $\mathcal{C}$8; and WNS/TNS correlation is NA or poor. SynCircuit with optimization improves the same setting to register-slack $\mathcal{C}$9, MAPE $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$0, RRSE $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$1; WNS $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$2, MAPE $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$3, RRSE $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$4; TNS $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$5, MAPE $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$6, RRSE $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$7; and area $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$8, MAPE $$\forall v_i \in V,\quad \mathrm{fanin}(v_i)=\mathrm{fanin\_req}(\mathrm{type}(v_i)),$$9, RRSE $\mathcal{C}(G)=0$0. The reported interpretation is that high-quality synthetic circuits can materially improve ML performance, especially when real data is scarce.

These results also delimit the framework’s intended use. The paper recommends synthetic data primarily as augmentation rather than replacement, and specifically recommends applying both constraint post-processing and MCTS optimization before using generated circuits in ML pipelines.

6. Comparisons, scope, and limitations

SynCircuit is compared with GraphRNN, DVAE, GraphMaker, and SparseDigress. GraphRNN and DVAE are described as requiring DAG structure, determining edge directions from topological order, and therefore being unable to produce cyclic structures characteristic of real sequential circuits. GraphMaker and SparseDigress generate undirected graphs; in the reported comparison, directions had to be assigned post hoc using Gravity-inspired Autoencoders, and most of the resulting logic was removed by synthesis. Against these baselines, SynCircuit is presented as the first framework targeted at RTL-level digital circuit generation via graph generative modeling and as the first diffusion-based solution explicitly designed for directed cyclic graphs, combining a forward process on adjacency, a directed MPNN encoder, and a relation-embedding-based asymmetric decoder (Liu et al., 26 Aug 2025).

The framework’s scope is explicitly limited. It focuses on synchronous digital RTL with registers as timing boundaries; more complex features such as multi-clock designs, asynchronous logic, memories, and large IPs are not explicitly addressed. Scalability is nontrivial because large graphs require careful MPNN design and MCTS over many cones is computationally demanding, although a PCS discriminator mitigates synthesis cost. The generative model is trained from real circuits, and the experiments use 22 designs; wider and more diverse training data are described as likely to improve generalization. High-level functional intent, such as complex protocols, is not explicitly controlled.

Future directions mentioned or implied include circuit foundation models, extension from RTL to logic-level/netlist generation and placement-and-routing graphs, increased expressiveness for multi-clock domains and memories, and tighter coupling with commercial and open-source EDA flows. A plausible implication is that SynCircuit occupies two roles simultaneously: it is both a data-generation system for AI for EDA and a graph generative modeling contribution specialized to circuit legality and post-synthesis realism.

7. Related synchronous, temporal, and synchronization-oriented frameworks

A separate line of work positions temporal computer organization as a basis for a SynCircuit framework in which data and computation are expressed as spike times rather than voltage levels or binary words. In that formulation, the value domain is

$\mathcal{C}(G)=0$1

segments are internally feedforward with feedback between segments, a gamma clock bounds each computational step and resets state, and functional completeness is recovered by allowing the gamma clock to act as a temporal reference input. The same account describes space-time algebra, synchronized segments, unit-time realignment, and a mapping to spiking neural networks and synfire-like chains (Smith, 2022).

Related circuit-oriented computation models also include the Synchronic A-Ram and the Space language. The Synchronic A-Ram is introduced as “a globally clocked, fine grained, simultaneous read, exclusive write machine” and is put forward as “the lowest level, formal model for FPGAs.” Space is described as a circuit-oriented, spatial programming language that is modular, strictly typed, deterministic, and largely referentially transparent, with programs compiling to Synchronic A-Ram machine code consisting of three bit-level instructions and a marking instruction (Berka, 2010).

At the timing-optimization level, VirtualSync+ proposes a timing model in which signals, especially along critical paths, are allowed to propagate through several sequential stages without flip-flops while boundary timing constraints are preserved. The reported result is circuit-performance improvement of up to 4% on average 1.5% beyond extreme retiming and sizing, with negligible area increase (Zhang et al., 2022).

In dissipative and quantum electrical networks, synchronization has been formalized through Poisson-Rayleigh brackets and Kirchhoff-Heisenberg equations. That framework derives native equations of motion for nonconservative circuits, studies synchronization in coupled resonators and weakly nonlinear resonators such as transmons, and introduces auxiliary circuit elements to regularize singular topologies (Mariantoni et al., 2024).

These adjacent lines of research do not redefine the 2025 RTL generator, but they show that SynCircuit sits within a broader technical landscape shaped by synchronization, timing, circuit-native formalism, and structured relations between computation and hardware. This suggests that the name can be read not only as a synthetic-data framework for RTL, but also as part of a wider vocabulary of synchronization-aware circuit research.