Dr. RTL: Agentic Framework for RTL Timing Optimization

• Dr. RTL is an agentic framework for RTL timing optimization that leverages industrial feedback to enhance post-synthesis PPA while maintaining design correctness.
• It employs a closed-loop multi-agent architecture combining timing analysis, parallel RTL rewriting, and formal SEC verification to select optimal design variants.
• Through group-relative skill learning, the framework builds a reusable library of transformation strategies to address critical timing bottlenecks in real-world Verilog designs.

Searching arXiv for the main paper and closely related RTL optimization work. arXiv.search({"query":"id:(Fang et al., 16 Apr 2026) OR title:\"Dr. RTL\" RTL optimization", "max_results": 5}) Searching for related RTL optimization and evaluation papers for context. arXiv.search({"query":"RTL optimization timing optimization Verilog agentic synthesis slack annotation RTL-Timer hardware design LLM", "max_results": 10}) Dr. RTL is an agentic framework for RTL timing optimization that operates in a tool-grounded, closed-loop setting and is explicitly designed for realistic post-synthesis improvement of human-written RTL rather than one-shot synthesis from scratch. It combines industrial EDA feedback, multi-agent critical-path analysis, parallel RTL rewriting, and continual self-improvement through a reusable skill library. In its reported evaluation, the framework is applied to 20 real-world RTL designs under commercial synthesis and sequential equivalence checking, and is presented as optimizing timing while preserving equivalence and original pipeline latency (Fang et al., 16 Apr 2026).

1. Problem scope and optimization objective

Dr. RTL is motivated by the observation that RTL quality constrains what downstream synthesis can achieve, so improving RTL itself can expose timing and area trade-offs that are not recovered by synthesis tuning alone. The work positions itself against evaluation settings based on manually degraded RTL, small toy modules, and weak open-source backends, arguing that such settings often reduce the problem to repairing artificial damage rather than optimizing already-strong designs (Fang et al., 16 Apr 2026).

The framework formulates RTL optimization as the search for an equivalent design $\mathcal{D}^*$ that improves post-synthesis PPA under correctness constraints:

$$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$

The primary timing metrics are WNS and TNS, and the current objective excludes power because accurate power evaluation is described as too workload-dependent for the static evaluation setting (Fang et al., 16 Apr 2026).

This places Dr. RTL in a different category from RTL synthesis and summarization systems. Contemporary RTL LLM work has emphasized generation, retrieval, and summarization, including graph-enhanced generation in RTL++ (Akyash et al., 11 May 2025), unified generation and embedding tasks in DeepRTL2 (Liu et al., 28 May 2025), stepwise reward-guided synthesis in StepPRM-RTL (Vijayaraghavan et al., 2 Jun 2026), and neuro-symbolic divide–retrieve–conquer synthesis and summarization in SYMDIREC (Vijayaraghavan et al., 17 Mar 2026). Dr. RTL instead targets post-synthesis optimization of existing RTL, with tool-evaluated timing feedback as the central signal.

2. Realistic evaluation environment and industrial flow

A defining feature of Dr. RTL is its evaluation environment. The reported benchmark consists of 20 original human-written Verilog designs drawn from real projects, spanning buffers, processors, DSP, crypto, SoCs, and control/datapath blocks. The paper reports an average of 812 LOC and 3 modules per design, with sizes ranging from 128 LOC to 4615 LOC (Fang et al., 16 Apr 2026).

The optimization loop is grounded in an industrial EDA workflow:

Element	Reported setup
Synthesis	Synopsys Design Compiler
Library	Nangate 45nm open cell library
Timing constraint	0.1 ns clock period
Verification	Cadence JasperGold Sequential Equivalence Checking

The use of Sequential Equivalence Checking (SEC) is central because the framework allows latency-preserving sequential restructuring rather than only combinational rewrites. The paper states that earlier methods using combinational equivalence checking or simulation could not robustly validate such transformations (Fang et al., 16 Apr 2026).

This emphasis on fine-grained timing feedback has a clear relation to earlier RTL-stage timing work. RTL-Timer addressed the lack of fine-grained timing information at RTL by predicting register-endpoint timing and reported average improvements of around 3.1% WNS and 9.9% TNS after optimization on unknown test designs (Fang et al., 2024). Dr. RTL differs in using actual post-synthesis critical-path reports inside a closed-loop rewrite-and-verify process rather than prediction alone.

3. Closed-loop multi-agent architecture

Dr. RTL is organized as an orchestrator + sub-agents system. Its iteration structure is

$$\mathcal{D}_t \rightarrow \{\mathcal{D}_t^{(i)}\}_{i=1}^N \rightarrow \mathcal{D}_{t+1},$$

where each round produces $N$ parallel RTL candidates, evaluates them with tools, and promotes the best SEC-passing candidate to the next iteration (Fang et al., 16 Apr 2026).

The three core agents are the timing analysis agent, the RTL optimization agent, and the evaluation agent. The orchestrator maintains a shared JSON state containing timing reports, candidate edits, evaluation outcomes, and iteration history.

The timing analysis agent reads the post-synthesis timing report, identifies the top-$k$ critical paths by slack, and maps those paths back to RTL regions through startpoint and endpoint registers, intermediate combinational logic, and likely structural sources of delay. The paper lists root-cause categories including excessive combinational depth, high fanout, control–data coupling, and reconvergent logic (Fang et al., 16 Apr 2026).

The RTL optimization agent generates candidates in parallel using equivalent RTL transformations. It first queries the skill library for a matching pattern–strategy entry; otherwise, the LLM proposes a new rewrite conditioned on timing feedback. This design makes critical-path-level diagnosis, rather than coarse design-level PPA, the primary steering signal (Fang et al., 16 Apr 2026).

The evaluation agent runs commercial synthesis and SEC and returns

$$(\text{WNS}_i, \text{TNS}_i, \text{Area}_i, \text{SEC}_i).$$

Candidate selection is performed by minimizing a scalar score over SEC-passing rewrites:

$$Score_i = \alpha\,\text{WNS}_i^{\text{norm}} + \beta\,\text{TNS}_i^{\text{norm}} + \gamma\,\text{Area}_i^{\text{norm}} + \text{penalty}_i$$

with reported weights $\alpha = 0.5$, $\beta = 0.35$, and $\gamma = 0.15$. The penalty is 0.5 if area increase exceeds 10%, otherwise 0. The next design is chosen as

$$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$0

This makes the decision rule explicitly tool-grounded rather than heuristic (Fang et al., 16 Apr 2026).

4. Group-relative skill learning and the skill library

A major contribution of Dr. RTL is group-relative skill learning, which converts optimization trajectories into reusable optimization knowledge. The paper argues that absolute PPA values are noisy and design-dependent, so candidate rewrites are judged relative to other candidates generated from the same parent design under the same timing context (Fang et al., 16 Apr 2026).

For candidate $$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$1 in iteration $$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$2, the relative advantage is defined as

$$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$3

where $$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$4 and $$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$5 are the mean and standard deviation of candidate scores in that iteration. This creates a within-group comparison signal for deciding which transformations are genuinely useful (Fang et al., 16 Apr 2026).

The skill-learning process is described as hierarchical at the iteration level, group level, and critical-path level. An auxiliary skill-learning agent extracts pattern–strategy pairs from these trajectories. The patterns are recurring timing bottlenecks such as deep FSM/decode logic, wide comparisons, mux-heavy selection, and high-fanout control signals. The strategies are recurring fixes such as condition pre-computation, decomposition, signal replication, and selective register insertion (Fang et al., 16 Apr 2026).

The resulting confidence-aware library $$\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0 .$$6 stores empirical statistics including occurrence count, SEC-pass count, and mean relative advantage. The paper reports that the current library contains 47 pattern–strategy entries, organized into 12 high-confidence strategies, 16 medium-confidence strategies, 6 low-confidence strategies, and 13 avoid strategies (Fang et al., 16 Apr 2026).

This reusable-memory design is a key point of departure from fixed-rule rewriting. A plausible implication is that Dr. RTL treats optimization knowledge as something accumulated from tool-grounded trajectories rather than specified ex ante.

5. Experimental protocol and quantitative results

The main experiments use 10 iterations per design, 5 parallel candidates per iteration, and 50 optimization attempts total per design. To test cross-design transfer, the paper uses 4-fold cross-validation: skills are learned from 15 designs and then applied to 5 unseen designs, with the library reset in each fold and prompts kept fold-isolated (Fang et al., 16 Apr 2026).

Across the 20 designs, the reported aggregate results are:

Metric	Reported result
Average WNS improvement	21.3%
Average TNS improvement	16.9%
Average area reduction	5.8%
Average SEC pass rate	86%

The paper also states that improvements were obtained on all 20 designs, with several especially large per-design gains: cpu_pipe improved WNS by 71.1%, TNS by 88.4%, with area down 11.8%; pcie improved WNS by 44.3%, TNS by 17.1%, with area down 33.9%; and lstm improved WNS by 25.3%, TNS by 30.3%, with area down 67.9% (Fang et al., 16 Apr 2026).

In the baseline comparison, using the same backbone model for fairness, the reported average improvements are approximately -2.4% WNS, -2.8% TNS, -0.7% area for Claude Opus single-shot; -1.2% WNS, +0.3% TNS, +0.6% area for GPT-5.3 single-shot; -4.9% WNS, -6.3% TNS, -3.1% area for RTLRewriter; -7.1% WNS, -5.7% TNS, -1.4% area for SymRTLo; and -21.3% WNS, -16.9% TNS, -5.8% area for Dr. RTL (Fang et al., 16 Apr 2026). In the paper’s framing, this indicates that commercial synthesis remains strong but does not remove the optimization opportunities exposed by structurally better RTL.

6. Position within RTL automation, misconceptions, and limitations

Dr. RTL addresses a common misconception in LLM-aided hardware design: that better RTL assistance is primarily a matter of generating modules from specifications. Much recent work has indeed focused on generation, summarization, and repository-scale completion, including large-context evaluation in RTL-Repo (Allam et al., 2024), graph-augmented generation in RTL++ (Akyash et al., 11 May 2025), and multi-task RTL assistance in DeepRTL2 (Liu et al., 28 May 2025). Dr. RTL instead targets the iterative engineering workflow in which an already functional RTL design is repeatedly analyzed, rewritten, and revalidated after synthesis feedback (Fang et al., 16 Apr 2026).

Another misconception is that the framework performs unconstrained architecture search. The paper is explicit that Dr. RTL preserves the original micro-architecture and pipeline latency, assumes fixed synthesis settings, and is oriented toward timing optimization, with area treated as a trade-off rather than the primary objective (Fang et al., 16 Apr 2026). Power is excluded from the current objective.

The reported runtime is dominated by EDA execution rather than LLM inference. In the experimental configuration, optimizing all 20 designs took about one week of wall-clock time and roughly \$50 in LLM usage (Fang et al., 16 Apr 2026). This suggests that the framework is practical only insofar as industrial tool throughput and parallel evaluation infrastructure are available.

More broadly, Dr. RTL can be read as a shift from prompt-level RTL assistance to optimization systems that are grounded in critical-path evidence and formal verification. This suggests a convergence between LLM-based code transformation, timing-driven design iteration, and reusable optimization memory. Within that framing, the framework’s central claim is not merely that an LLM can rewrite Verilog, but that tool-grounded self-improvement can make iterative RTL optimization a cumulative process rather than a sequence of isolated edits (Fang et al., 16 Apr 2026).