Variable Topology Circuits

• Circuits with variable topology are systems where the connection architecture is dynamically modulated, enabling flexible design and reconfiguration across technology domains.
• They encompass regimes such as reconfigurable electrical hardware, topolectrical networks, variational quantum circuits, and textile logic, each optimizing unique performance invariants.
• Methodologies include runtime switching, dynamic coupling modulation, and AI-driven synthesis to enhance fault tolerance and optimize circuit performance.

Circuits with variable topology are systems in which the interconnection structure, effective coupling graph, or admissible circuit architecture is not fixed a priori, but is instead designed, synthesized, reconfigured, or dynamically modulated. In contemporary research this notion spans several distinct but related regimes: reconfigurable electrical hardware whose switch states physically change converter connections, topolectrical networks whose graph connectivity and grounding determine the topology of admittance bands, variational and synthesized circuits whose architecture is searched over rather than preset, and topology-defined mechanical or textile circuits in which logical behavior is encoded by linkage rather than geometry (Lee et al., 2017, Li et al., 2017, Cheng et al., 2022, Shimamoto, 12 Jun 2026).

1. Meanings of topology in circuit research

Across the literature, “topology” refers to more than one object. In some papers it means the physical interconnection of branches and nodes; in others it means the topological class of an effective Hamiltonian or Floquet operator; in still others it denotes a discrete design object such as a quantum ansatz graph or a netlist. A common misconception is that variable topology always means literal rewiring during operation. The published work shows a broader taxonomy: design-time graph variation, runtime switch-based reconfiguration, field-programmable effective couplings, and topology-defined computation in non-electronic media (Lee et al., 2017, Huang et al., 2020).

Regime	What varies	Representative source
Topolectrical networks	Connectivity, grounding, admittance-band topology	(Lee et al., 2017)
Reconfigurable power converters	DC/AC-side interconnection structure	(Li et al., 2017)
Variational quantum circuits	Ansatz architecture and entangling graph	(Cheng et al., 2022)
LLM-based circuit synthesis	Netlist or graph itself	(Vijayaraghavan et al., 2024)
Field-programmable topological arrays	Local fields, phases, topological segments	(Huang et al., 2020)
Knitted mechanical circuits	Stitch topology and release pathways	(Shimamoto, 12 Jun 2026)

This multiplicity matters because different communities optimize different invariants. In power electronics, the principal object is converter functionality under switch-controlled rearrangement. In topolectrical physics, graph topology and band topology coexist: one engineers the first to realize the second. In quantum architecture search and AI synthesis, the topology is a combinatorial object over which one searches. In textile logic, topology is the invariant of a yarn linkage pattern rather than a graph embedded on a PCB.

2. Graph topology and band topology in topolectrical networks

In topolectrical circuits, the foundational object is the grounded circuit Laplacian. For a time-harmonic drive, Kirchhoff’s law takes the form

$I=(L+W)V \equiv JV,$

where $L=D-C$ is the circuit Laplacian built from the conductance adjacency matrix $C$ and degree matrix $D$, and $W$ is the grounding matrix. Its eigenmodes satisfy $J\psi_n=j_n\psi_n$, and the two-point impedance can be written as

$$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$

Because $J$ is determined by graph connectivity, component values, and grounding, changing any of these changes the effective Hamiltonian and hence the topology of the admittance spectrum. The canonical example is the SSH circuit with alternating capacitors $C_1,C_2$ and grounding inductors $L$, whose winding number is $L=D-C$0. At the resonant frequency $L=D-C$1, the midgap boundary mode is tuned near zero admittance, producing a topological boundary resonance in impedance (Lee et al., 2017).

The general theory was subsequently extended from specific SSH-like constructions to arbitrary Hermitian tight-binding models in LC networks. By replacing each node with $L=D-C$2 subnodes whose phases are the $L=D-C$3 distinct roots of unity and using shift capacitor couplings, one can realize arbitrary complex Hermitian hopping amplitudes. In this framework, two-subnode constructions implement $L=D-C$4 hoppings, four-subnode constructions implement phases in $L=D-C$5, and stacked topolectric circuits realize first-order, second-order, and third-order topological insulators as well as Weyl, nodal-loop, quadrupolar Dirac, and Weyl semimetals. The associated impedance signatures localize on boundaries of codimension $L=D-C$6 for an $L=D-C$7-th order phase (Dong et al., 2020).

A complementary LC design language emphasizes loops, stars, permutation wiring, and $L=D-C$8-shift connections. There the key variables are not only capacitances and inductances but the wiring permutations between multi-terminal building blocks. Emergent pseudospin degrees of freedom and synthetic gauge fields arise from these permutations, enabling the SSH transmission line, the braided $L=D-C$9-flux ladder, the circuit analog of Haldane’s Chern insulator, and a four-dimensional quantum Hall analog with finite second Chern number. In this construction the relevant topology is explicitly not the shape of wires in space but the graph of connections and its induced dynamical $C$0-matrix (Zhao, 2018).

Review work has broadened this picture further by surveying non-Hermitian, nonlinear, non-Abelian, non-periodic, non-Euclidean, and higher-dimensional topolectrical states, while stressing the role of flexible interconnections and compatibility with traditional integrated circuits. This suggests that topolectrical circuits are a paradigmatic variable-topology platform because a single graph-theoretic design freedom simultaneously controls physical connectivity, spectral structure, and experimentally measurable boundary localization through impedance or voltage response (Yang et al., 2024).

3. Runtime reconfiguration in hardware platforms

In power electronics, topology means the interconnection of semiconductor devices, sources, and loads. Li and Shek proposed two reconfigurable converter topologies that automatically transform a three-phase 3-level cascaded H-bridge inverter with six separate 48 V DC sources into a three-phase 2-level bridge inverter by flicking specific switches controlled by step signals at $C$1. The two designs reroute both DC-side and AC-side connections by means of ideal switches and, where needed, 3-way switches. In 2-level mode, topology 1 shows a phase voltage difference of about $C$2, whereas topology 2 shows about $C$3. They also show that when one upper DC source is opened or shorted, the 3-level output of topology 1 is compromised while the 2-level mode remains almost unchanged, making reconfiguration a fault-tolerant operating mode rather than merely a geometric curiosity (Li et al., 2017).

At a finer scale, the field-programmable topological array adopts an FPGA-like logic: the hardware layout is fixed, but its topological function is defined at run time by programming local fields. The proposed control cells independently and simultaneously tune electrostatic fields, magnetic fields, effective spin-orbit fields, and superconducting properties such as pair potential, superfluid density, and superconducting phase. On semiconductor–superconductor platforms, this enables one to turn segments topological or trivial, create or annihilate Majorana zero modes, modulate couplings between them, and shape synthetic Andreev-bound-state band structures with Weyl points. The case studies include crossed Andreev reflection enhancement, one-dimensional topological phase transitions, non-Abelian manipulations, and synthetic Weyl-point engineering (Huang et al., 2020).

Topolectrical space-time circuits move from discrete switching to continuous space-time modulation of couplings. Their central hardware element is a time-varying impedance converter via current inversion, controlled by external voltages, such that the node-voltage dynamics takes the same form as a time-dependent Schrödinger equation. The resulting networks satisfy discrete space-time translational symmetries and experimentally realize a $C$4-dimensional topological space-time crystal with midgap edge modes, a $C$5-dimensional topological space-time crystal with chiral edge states, and $C$6-dimensional Weyl space-time semimetals. Here variable topology is realized not by breaking or making bonds outright, but by driving a periodic sequence of effective weighted adjacency matrices whose full space-time pattern carries the topological invariant (Zhang et al., 23 Jan 2025).

4. Architecture search in variational quantum circuits

In variational quantum algorithms, variable topology appears as ansatz synthesis rather than physical rewiring. TopGen addresses this by abandoning a fixed, monolithic ansatz template and generating topology-specific ansätze bottom-up from sub-circuits that are explicitly matched to the hardware coupling graph. The target device is modeled as a graph $C$7, connected subgraphs of size 2–4 are extracted, and only hardware-compatible gates are allowed: $C$8 on each qubit and CNOTs only on device edges. Sub-circuits are ranked by expressibility, measured through KL divergence between the induced fidelity distribution and the Haar distribution, and by entangling capability, quantified through the Meyer–Wallach global entanglement $C$9.

The global ansatz is then assembled from these local blocks. Two mechanisms make its topology genuinely variable. First, stitching inserts extra inter-block two-qubit gates between neighboring sub-circuits, changing the entanglement graph rather than merely reweighting parameters. Second, dynamic circuit growing appends “appendable” sub-circuits whose unitary is the identity at zero initialization, allowing the graph of interactions to expand during training without restarting optimization. In this framework, topology varies at the sub-circuit level, at the level of placement across the device, and temporally during optimization.

The empirical results are explicitly hardware-centered. On 14 machine-learning tasks, the TopGen-searched ansatz can reduce circuit depth and the number of CNOT gates by up to $D$0 and $D$1, respectively, under the same performance. After compilation to IBM hardware, baseline ansätze average depth $D$2, $D$3gates $D$4, and $D$5CNOTs $D$6, whereas TopGen-derived ansätze reach compiled depths of 18–22 with $D$7CNOTs consistently around 4. Experiments on ibmq_quito, ibmq_lima, and ibm_oslo report on average 17% accuracy improvements over baselines, primarily because topology-aware synthesis eliminates many SWAPs and reduces noise exposure (Cheng et al., 2022).

5. Automated synthesis and bidirectional design

A different interpretation of variable topology treats the circuit itself as a discrete combinatorial object to be generated. CIRCUITSYNTH operates in this regime. It considers a power-converter domain with 5 device components, each with 2 ports, plus 3 external ports IN, OUT, and 0, giving 13 ports to interconnect. Circuit topology is represented as an undirected graph and serialized as incident-encoded text. The model is trained on 862,606 circuits generated by Random Search and filtered by NGSpice, of which 567,307 are valid and 295,299 invalid. Its two-phase pipeline consists of topology generation by a fine-tuned decoder-only LLM and topology refinement using a pretrained validity classifier, a composite loss

$D$8

and a Gumbel–Softmax straight-through relaxation so gradients from the validity model can flow back through discrete netlist tokens. For GPT-Neo, refinement increases SPICE validity from 0.60 to 0.648, average efficiency from 0.692 to 0.713, and lowers duplicate generation rate $D$9 from 1.89 to 1.31; for StableLM, SPICE validity rises from 0.591 to 0.624 and efficiency from 0.682 to 0.728 (Vijayaraghavan et al., 2024).

In topological-circuit design, a related but distinct framework performs bidirectional multimodal generation for 2D SSH topolectrical circuits. It uses ImageBind to encode circuit diagrams, absorption maps, and structured text into a shared space, aligns those features with Vicuna 2, and then decodes through Stable Diffusion. The dataset contains 8,200 text entries and 12,400 images. Forward mode predicts node-absorption distributions from a circuit structure and operating frequency; reverse mode generates a circuit structure and operating frequency from a target absorption pattern. The framework is demonstrated on 2D SSH circuits with 4 sites per unit cell and reports 94% accuracy for reverse design of circuit structures and forward prediction of topological edge states, with PCB fabrication and experimental absorption measurements used for verification (Chen et al., 2024).

These AI-driven approaches make a useful distinction. CIRCUITSYNTH searches static netlist space under validity constraints, whereas the bidirectional 2D SSH framework learns correspondences between structural patterns and edge-state observables in a fixed model family. A plausible implication is that “variable topology” in automated design spans at least two tasks: unrestricted graph generation and inverse design within a constrained topological phase diagram.

6. Abstract formulations and topology-defined logic

The broadest formal separation between topology and element law appears in projective circuit theory. There each branch satisfies the homogeneous relation

$W$0

and a general linear circuit with $W$1 uncoupled two-terminal elements reduces to

$W$2

with branch currents and voltages recovered as

$W$3

Here $W$4 and $W$5 encode only graph topology, while $W$6, $W$7, and $W$8 encode homogeneous descriptions of the elements. Non-degenerate source-free configurations are characterized by the multihomogeneous Kirchhoff polynomial

$W$9

whose monomials are indexed by spanning trees. This framework is specifically designed to remain valid across impedances, admittances, ideal sources, opens, shorts, and partially homogeneous hybrids without changing the underlying algebraic form (Riaza, 2018).

A related but different abstraction is Gluskin’s structural superposition theory for one-ports of fixed topology. An $J\psi_n=j_n\psi_n$0-circuit with branch law

$J\psi_n=j_n\psi_n$1

is constructed as an $J\psi_n=j_n\psi_n$2-connection of $J\psi_n=j_n\psi_n$3-circuits of the same topology, each satisfying $J\psi_n=j_n\psi_n$4. The input map $J\psi_n=j_n\psi_n$5, with $J\psi_n=j_n\psi_n$6, is then observed to be close to linear: $J\psi_n=j_n\psi_n$7 is well approximated by the sum of the input characteristics of the isolated $J\psi_n=j_n\psi_n$8-circuits. The paper analyzes explicit cases $J\psi_n=j_n\psi_n$9 and $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$0, and also identifies topologies in which the superposition becomes exact because the internal node voltages are independent of $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$1 (Gluskin, 2010).

The notion of topology can even move outside electronics. In topology-defined computation in knitted textiles, the circuit is a single continuous yarn discretized into cells with topological state variable $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$2, where $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$3 denotes knitted and $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$4 unraveled. Logic bits are encoded by two-cell pairs, propagation is governed by prerequisite sets $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$5, and the global update is monotone: cells can transition from $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$6 to $$Z_{ab}=\sum_{j_n\neq 0}\frac{|\psi_{n,a}-\psi_{n,b}|^2}{j_n}.$$7 but not back. On this basis the system realizes NOT, AND, OR, and a half-adder. A key result is that geometric deformation changes whether the computation can be executed, but not the logical output prescribed by the topology of the stitch network; order-independent convergence to the same terminal configuration follows from the monotone update structure (Shimamoto, 12 Jun 2026).

Taken together, these lines of work show that circuits with variable topology are not a single device class but a family of methodologies. The invariant theme is the elevation of connectivity, linkage, or effective coupling pattern to a primary design variable. In some settings that variable is rewired physically; in others it is compiled into a circuit Laplacian, searched over as a netlist, modulated in space-time, programmed by local fields, or encoded in the topology of a yarn. The result is a unified but plural concept: circuit behavior is controlled not only by parameter values on a fixed graph, but by deliberate variation of the graph, the admissible architecture, or the topological class of the resulting dynamics.