Signal Timing Dependency Graph (STDG)

• STDG is a graph-based circuit representation that couples register, signal, and combinational elements with embedded timing semantics including delays and slacks.
• It is constructed by integrating Verilog netlists with static timing reports, ensuring traceability to source code and enabling precise delay and slack computations.
• In multi-cycle fault prediction, STDG extends to a spatio-temporal model, supporting dynamic edge features for efficient cycle-based predictions and test optimization.

Searching arXiv for the cited papers to ground the article. Search query: arXiv (Lv et al., 18 Aug 2025) ViTAD Timing Violation-Aware Debugging of RTL Code using LLMs Signal Timing Dependency Graph (STDG) denotes a graph-based circuit representation in which structural connectivity is coupled to timing semantics. In one explicit formulation, introduced in the context of RTL timing-violation debugging, the STDG is a weighted, directed graph $G=(V,E,w,\mu)$ whose nodes represent register-elements, signals or wires, and combinational-logic elements, while edges encode data, control, or clock dependencies together with propagation delays and optional slack annotations (Lv et al., 18 Aug 2025). In a related formulation for multi-cycle fault prediction, the same functional role is realized by a spatio-temporal graph that combines static gate-and-wire topology with cycle-indexed dynamic edge features (Wei et al., 8 Sep 2025). Taken together, these formulations position the STDG as an intermediate representation for timing-aware analysis, root-cause localization, and downstream electronic design automation workflows.

1. Definition and representational scope

The two cited uses of the STDG concept differ in granularity and objective, but both encode circuit structure together with timing-relevant information. In ViTAD, the representation is explicitly called a Signal Timing Dependency Graph and is used to bridge Verilog source, static timing analysis, and LLM-guided debugging (Lv et al., 18 Aug 2025). In the spatio-temporal GNN work, the authors refer to their structure as an ST-Graph, but the provided description states that it fulfills exactly the role of an STDG by combining static topology with dynamic, multi-cycle signal-propagation behavior (Wei et al., 8 Sep 2025).

Aspect	ViTAD formulation	ST-GCN formulation
Base object	Weighted, directed graph $G=(V,E,w,\mu)$	Spatial graph $G_s=(V,E_s)$ plus temporal graph $G_t=(V_t,E_t)$
Primary entities	Registers, signals/wires, combinational elements	Logic gates and flip-flops
Timing semantics	Per-edge propagation delay and register slack	Time-indexed dynamic edge features over successive cycles

This comparison suggests that STDG is best understood as a representational pattern rather than a single canonical encoding. In both cases, a plain connectivity graph is insufficient: timing or temporal annotations are part of the representation itself, not an external supplement. A common reduction is to treat such graphs as mere netlists; the cited formulations instead embed dependency type, delay, slack, or cycle-varying features directly into the graph object.

2. Formal graph model in RTL timing analysis

In the ViTAD formulation, the STDG is defined as a weighted, directed graph

$G=(V,E,w,\mu),$

where $V$ is partitioned into three disjoint node sets: $R=\{r_1,r_2,\dots\}$ for register-elements, $S=\{s_1,s_2,\dots\}$ for signals or wires, and $C=\{c_1,c_2,\dots\}$ for combinational-logic elements such as gates, multiplexers, and instances (Lv et al., 18 Aug 2025). The edge set $E\subseteq V\times V$ is directed, and each edge $G=(V,E,w,\mu)$0 carries a dependency type $G=(V,E,w,\mu)$1. Data-dependency edges link a driver node to a consumer, control-dependency edges connect, for example, a select signal to a multiplexer element, and clock-dependency edges may connect a clock source to a register for setup or hold analysis.

The weighting function $G=(V,E,w,\mu)$2 assigns each edge a nonnegative propagation delay $G=(V,E,w,\mu)$3 in nanoseconds as reported by static timing analysis. The optional mapping $G=(V,E,w,\mu)$4 assigns slack information to register nodes, with

$G=(V,E,w,\mu)$5

where $G=(V,E,w,\mu)$6 is the required arrival time from the report. Each node also carries attributes including $G=(V,E,w,\mu)$7, $G=(V,E,w,\mu)$8, $G=(V,E,w,\mu)$9, and possibly arrival time $G_s=(V,E_s)$0 computed during analysis.

For a register-to-register path

$G_s=(V,E_s)$1

with $G_s=(V,E_s)$2 as the launch register and $G_s=(V,E_s)$3 as the capture register, ViTAD uses

$G_s=(V,E_s)$4

This construction makes the STDG a timing-bearing dependency graph rather than a syntactic RTL graph. Because node attributes include $G_s=(V,E_s)$5, every graph element can also be traced back to a Verilog file and line.

3. Construction from Verilog and timing reports

ViTAD constructs the STDG algorithmically from Verilog code and static timing reports (Lv et al., 18 Aug 2025). The high-level procedure is: parse the Verilog code to an Abstract Syntax Tree using Pyverilog or similar; extract the netlist consisting of registers, wires, and combinational instances; build an initial unweighted graph of pure RTL connectivity; parse the STA timing report, such as a Vivado .rpt, to extract per-path and per-arc delays and slacks; and then map each delay entry back onto the corresponding edge or edges in $G_s=(V,E_s)$6 while labeling destination registers with slack.

The construction process is explicit about dependency typing. Register declarations create register nodes and, where appropriate, clock-dependency edges from the clock signal to the register. Assignment statements and instances create data-dependency edges from input nets to combinational instances and from instances to output nets. Combinational blocks with select or control signals create control-dependency edges from those signals to the instance. Timing-report entries are then matched to graph paths so that edge weights become per-arc delays and register annotations become slack values.

A five-line Verilog example in the ViTAD description illustrates the resulting graph. The module contains a multiplexer controlled by sel, an AND stage, and a register y. The constructed STDG has nodes

$G_s=(V,E_s)$7

with $G_s=(V,E_s)$8 and $G_s=(V,E_s)$9 as combinational-element nodes and $G_t=(V_t,E_t)$0 as the register storing $G_t=(V_t,E_t)$1. Its edges include $G_t=(V_t,E_t)$2 with $G_t=(V_t,E_t)$3 and $G_t=(V_t,E_t)$4, $G_t=(V_t,E_t)$5 with $G_t=(V_t,E_t)$6 and $G_t=(V_t,E_t)$7, $G_t=(V_t,E_t)$8 with $G_t=(V_t,E_t)$9, $G=(V,E,w,\mu),$0 with $G=(V,E,w,\mu),$1, and $G=(V,E,w,\mu),$2 with $G=(V,E,w,\mu),$3 and $G=(V,E,w,\mu),$4.

Under the assumptions $G=(V,E,w,\mu),$5 and an STA-reported total delay of $G=(V,E,w,\mu),$6 from a to $G=(V,E,w,\mu),$7, the path delay is computed as

$G=(V,E,w,\mu),$8

and the slack is

$G=(V,E,w,\mu),$9

which is a setup violation. The example is small, but it shows that the graph simultaneously records structural causality, timing numerics, and source-code traceability.

4. Violation-path extraction and LLM-guided debugging

Once the graph is built and every register node $V$0 has slack $V$1, ViTAD locates all registers satisfying $V$2 and extracts the violation paths leading into them (Lv et al., 18 Aug 2025). Let

$V$3

be the set of violating registers. For each $V$4, the method performs a backward traversal from the violating register to any source register or primary input. Because the graph is acyclic for pure combinational plus register structure, ViTAD topologically sorts the graph and then applies dynamic programming:

$V$5

with boundary condition $V$6 for any source $V$7. The maximal value at $V$8 is exactly the delay of the longest path into the violating register. The critical path is then recovered by back-tracking the maximizing predecessor choices:

$V$9

The complexity of this extraction procedure is linear in graph size: topological sorting is $R=\{r_1,r_2,\dots\}$0, one dynamic-programming pass is $R=\{r_1,r_2,\dots\}$1, and path reconstruction is $R=\{r_1,r_2,\dots\}$2. The description therefore states that extracting the critical longest path is $R=\{r_1,r_2,\dots\}$3.

Within the ViTAD flow, the STDG is the single unified data structure that encodes both RTL structural connectivity and per-arc or per-node timing. Violation-path extraction yields an explicit sequence of signals, gates, and registers with numeric delays and slacks; that sequence, together with source-code snippets at each node’s src_loc, forms the root-cause description fed to the LLM. After the LLM returns a root-cause rationale in natural language, that rationale is used to retrieve scenario-specific repair knowledge from a domain-specific knowledge base and to drive the template engine that generates a targeted patch. In the overall evaluation on a timing-violation dataset containing 54 cases from real-world open-source projects, the method achieved a 73.68% success rate in repairing timing violations, compared with 54.38% for the baseline using only an LLM, an improvement of 19.30%.

5. Spatio-temporal generalization for multi-cycle fault prediction

A distinct but related formulation appears in the ST-GCN framework for predicting silent data corruption inducing circuit-level faults (Wei et al., 8 Sep 2025). There, the representation is decomposed into a spatial graph and a temporal graph. The spatial graph is

$R=\{r_1,r_2,\dots\}$4

where $R=\{r_1,r_2,\dots\}$5 is the set of nodes and $R=\{r_1,r_2,\dots\}$6 is the set of undirected or directed edges corresponding to physical signal lines connecting gates. The adjacency matrix $R=\{r_1,r_2,\dots\}$7 encodes this connectivity through

$R=\{r_1,r_2,\dots\}$8

The temporal graph is

$R=\{r_1,r_2,\dots\}$9

with temporal edges

$S=\{s_1,s_2,\dots\}$0

Each physical node is thus unrolled into a node-time pair $S=\{s_1,s_2,\dots\}$1, producing $S=\{s_1,s_2,\dots\}$2 temporal nodes. Temporal edges link gates at the same cycle along the same physical nets but carry dynamic features that evolve with $S=\{s_1,s_2,\dots\}$3. In effect, the temporal graph is a time-series of copies of the spatial graph, each annotated by the edge-feature snapshot at that cycle.

The node set represents logic elements such as AND, OR, NOT, and D-FF, and each node carries a static one-hot gate-type feature

$S=\{s_1,s_2,\dots\}$4

Edges represent wires. In the temporal view, each edge $S=\{s_1,s_2,\dots\}$5 is annotated at cycle $S=\{s_1,s_2,\dots\}$6 by a dynamic feature vector $S=\{s_1,s_2,\dots\}$7. Two feature strategies are described. In the testability-metrics-based strategy,

$S=\{s_1,s_2,\dots\}$8

where $S=\{s_1,s_2,\dots\}$9 and $C=\{c_1,c_2,\dots\}$0 are 0- and 1-controllability, $C=\{c_1,c_2,\dots\}$1 is observability, and the values of $C=\{c_1,c_2,\dots\}$2, $C=\{c_1,c_2,\dots\}$3, and $C=\{c_1,c_2,\dots\}$4 are min–max normalized across the graph before learning. In the fault-simulation-based strategy, $C=\{c_1,c_2,\dots\}$5 is the ground-truth Fault Impact Probability of a stuck-at, transition, or delay fault on the net at cycle $C=\{c_1,c_2,\dots\}$6.

Before convolution, node and edge features are embedded into a common $C=\{c_1,c_2,\dots\}$7-dimensional space:

$C=\{c_1,c_2,\dots\}$8

where $C=\{c_1,c_2,\dots\}$9 and $E\subseteq V\times V$0 are learnable and $E\subseteq V\times V$1 may be sinusoidal or learned positional embeddings.

The model then applies a two-branch encoder and a joint decoder. The spatial branch performs a gated graph convolution over $E\subseteq V\times V$2 using the temporally encoded edge features. The temporal branch uses a Graph Transformer with global attention to refine node embeddings at each cycle. The joint decoder sums the spatial and temporal outputs per cycle,

$E\subseteq V\times V$3

aggregates the sequence over the $E\subseteq V\times V$4 cycles by attention, and predicts future values through

$E\subseteq V\times V$5

6. Analytical role, performance, and limitations

The two formulations use the STDG for different analytical targets. In ViTAD, the graph is used for timing-violation root-cause analysis and repair generation. Its stated benefits are traceability, because each timing arc maps back to a precise Verilog source location; completeness, because both data and control dependencies are present; quantitative grounding, because slack and delay values are explicit; and efficiency, because critical-path extraction scales linearly in design size (Lv et al., 18 Aug 2025). The same description also enumerates limitations: the graph is static only and does not capture dynamic effects such as clock skew variation, crosstalk, or multi-cycle paths; cell-level details such as library parasitics may be folded or approximated; and very large designs may produce huge STDGs requiring pruning or slice extraction.

In the ST-GCN setting, the graph is used to predict long-cycle fault impact probabilities and to support downstream test strategy optimization. The fault impact probability for fault $E\subseteq V\times V$6 on net $E\subseteq V\times V$7 at cycle $E\subseteq V\times V$8 is defined as

$E\subseteq V\times V$9

where the indicator $G=(V,E,w,\mu)$00 is $G=(V,E,w,\mu)$01 if the fault is observed under pattern $G=(V,E,w,\mu)$02 and $G=(V,E,w,\mu)$03 otherwise (Wei et al., 8 Sep 2025). Training minimizes the multi-step mean squared error

$G=(V,E,w,\mu)$04

and evaluation uses RMSE and MAE. On ISCAS-89 benchmarks, the method reduces simulation time by more than $G=(V,E,w,\mu)$05 while maintaining high accuracy, with mean absolute error $G=(V,E,w,\mu)$06 for 5-cycle predictions in the abstract and MAE as low as $G=(V,E,w,\mu)$07 for 5-cycle horizons and approximately $G=(V,E,w,\mu)$08 for 10-cycle predictions in the detailed description. In a test-point insertion case study using 2% of D-FFs as scan-like observation points, the STDG-based greedy selection reduces the number of cycle-sensitive faults far more rapidly than random insertion, as measured by the average FIP curve over 10 cycles.

A plausible implication is that the STDG concept supports two complementary regimes of timing-aware reasoning. The ViTAD formulation emphasizes explainable, source-linked diagnosis under static timing analysis, whereas the spatio-temporal formulation emphasizes learned prediction of multi-cycle behavior from graph-structured circuit data. Both cases depend on the same core idea: topology alone is insufficient, and timing semantics must be integrated into the graph itself.