CircuitGCL: Graph Contrastive Learning in AMS Circuits

Updated 6 July 2026

CircuitGCL is a framework for transferable parasitic estimation in AMS circuits, using topology-invariant node embeddings to generalize across designs.
It integrates self-supervised contrastive pretraining with label-rebalanced supervised objectives for both edge regression and node classification.
Empirical results show significant gains in R² and F1 scores while reducing resource usage compared to heavy positional encoding methods.

Searching arXiv for the specified CircuitGCL paper and closely related AMS-circuit graph learning work to ground the article. {"query":"arXiv (Shen et al., 9 Jul 2025) CircuitGCL parasitic estimation AMS circuits CircuitGPS DLPL-Cap ParaGraph", "max_results": 10} I found the following relevant arXiv papers:

"Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits" (Shen et al., 9 Jul 2025)
"Few-Shot Learning with Positional Encoding for Scalable Circuit Representation and Parasitic Prediction" (Sonoda et al., 5 May 2025)
"Deep Learning Prediction of Layout-to-Schematic Parasitic Capacitance for Analog Circuits" (Usuba, 24 Jan 2025)
"CircuitNet: Towards Scalable Graph Learning in Circuit Design" (Sumbul et al., 2023)

Searching for the ParaGraph baseline to determine whether it has an arXiv version suitable for citation. {"query":"ParaGraph MPNN ensemble parasitic capacitance arXiv", "max_results": 10} I found the following relevant arXiv papers:

"Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits" (Shen et al., 9 Jul 2025)
"A Deep Learning Framework for Optimization of Functional Circuits Using Graph Theory" (Lopes et al., 22 May 2025)
"Semi-Supervised Graph Machine Learning for Amplifier Design" (Mandlmayr et al., 2024)
"Synthetic-to-Real Generalization on Board-level Circuit Graphs" (Laha et al., 2023)

Searching for the DLPL-Cap baseline to verify whether it corresponds to an arXiv paper. {"query":"DLPL-Cap arXiv parasitic capacitance analog circuits", "max_results": 10} I found the following relevant arXiv papers:

"Deep Learning Prediction of Layout-to-Schematic Parasitic Capacitance for Analog Circuits" (Usuba, 24 Jan 2025)
"Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits" (Shen et al., 9 Jul 2025)
"Few-Shot Learning with Positional Encoding for Scalable Circuit Representation and Parasitic Prediction" (Sonoda et al., 5 May 2025)

CircuitGCL denotes a graph contrastive learning framework for transferable parasitic estimation in Analog-Mixed Signal (AMS) circuits. It was introduced to address three coupled difficulties in circuit graph learning: scarce proprietary design data, long-tailed and design-dependent label distributions, and strong heterogeneity across analog, digital, and mixed-signal implementations. In its primary formulation, CircuitGCL learns topology-invariant node embeddings through self-supervised pretraining on a single design, then applies label-rebalanced supervised objectives for edge-level parasitic capacitance regression and node-level ground capacitance classification, with strict zero-shot transfer to unseen TSMC 28nm designs (Shen et al., 9 Jul 2025).

1. Problem formulation and scope

CircuitGCL is designed for AMS parasitic estimation under cross-design distribution shift. The stated failure mode of conventional supervised GNNs is overfitting to a single design’s topology and label statistics, which reduces transfer when the test design differs in both implementation style and parasitic distribution. The framework therefore combines two components: a self-supervised representation learner intended to produce topology-invariant embeddings, and supervised objectives that explicitly compensate for label imbalance in both regression and classification (Shen et al., 9 Jul 2025).

The targeted downstream tasks are distinct. The edge-level task is pre-layout estimation of coupling capacitance between nets or pins, treated as a continuous regression problem. The node-level task is categorization of ground capacitance on nets into discrete ranges, treated as a classification problem. The underlying claim is not merely that a single encoder can serve both tasks, but that the same pretraining strategy can generate reusable embeddings that transfer to unseen designs without task-specific fine-tuning. This suggests that CircuitGCL is positioned less as a task-specific predictor than as a transferable representation-learning pipeline for AMS EDA.

2. Circuit graph abstraction and data protocol

CircuitGCL begins from a schematic netlist converted into a graph $G=(V,E)$ with node set $V$ and adjacency $A$ . The node vocabulary consists of nets, transistor devices, and pins. Edges encode device-to-pin and net-to-pin connectivity. The parasitic quantities of interest are not included directly as graph edges in $E$ ; instead, coupling edges such as pin-to-net, pin-to-pin, and net-to-net are modeled as candidate targets for edge regression (Shen et al., 9 Jul 2025).

To enable homogeneous GNN processing, heterogeneous circuit graphs are converted to homogeneous graphs by encoding node type as a categorical attribute $X \in \{0,1,2\}^{N \times 1}$ . The method does not require edge attributes. In the reported experiments, general node features described as circuit statistics are also extracted as in prior work. No positional encoding is required. This design choice is central to the method’s positioning, because CircuitGCL is explicitly presented as replacing heavy positional encodings such as DSPD with learned embeddings obtained through contrastive pretraining.

The evaluation protocol is unusually strict for AMS parasitic prediction. Training and validation are performed on a single mid-sized TSMC 28nm design, and testing is performed in zero-shot fashion on multiple unseen designs, including DIGITAL_CLK_GEN, TIMING_CONTROL, ARRAY_128_32, ULTRA8T SRAM, and SANDWICH-RAM. Label distributions are described as highly skewed and design-dependent. For scalability, mini-batches are formed with PyG LinkNeighborLoader, which constructs link-neighborhood subgraphs during training.

3. Architecture and hyperspherical representation scattering

The pretraining stage uses a graph contrastive learning configuration with a target encoder $f_{\phi}(\cdot)$ , an online encoder $f_{\theta}(\cdot)$ , and a predictor $q_{\theta}(\cdot)$ . The encoder backbone for pretraining is a 4-layer ClusterGCN with hidden dimension 256, Tanh activation, dropout 0.3, and learning rate $10^{-6}$ . Downstream supervised models use GraphSAGE: a 5-layer, hidden-144, PReLU, dropout-0.3 model for edge regression, and a 4-layer counterpart for node classification, both trained with learning rate $10^{-4}$ . Task heads are 2-layer MLPs matched to the hidden sizes of the respective backbones (Shen et al., 9 Jul 2025).

The distinctive pretraining mechanism is hyperspherical representation scattering, also called the Representation Scattering Mechanism (RSM). Node embeddings are projected to the unit hypersphere,

$V$ 0

A scatter center is then defined as

$V$ 1

and the scattering loss is

$V$ 2

The mechanism has two stated effects: a center-away constraint that pushes representations away from the scatter center, and a uniformity constraint that distributes them across the hypersphere. The intended result is a topology-invariant embedding space in which functionally similar nodes cluster while distinct nodes separate. The reported training recipe also includes a BGRL-style alignment loss without explicit negatives,

$V$ 3

and an EMA update for the target encoder,

$V$ 4

The pretraining objective is

$V$ 5

A recurrent misconception is to treat CircuitGCL as a conventional augmentation-heavy graph contrastive method. Its formulation is the opposite: it does not perturb circuit topology, does not require negative sampling, and relies instead on hyperspherical uniformity plus EMA-stabilized alignment. The paper argues that manual graph augmentations can bias circuit semantics by altering topology, whereas CircuitGCL attempts to retain topology while learning an embedding geometry that generalizes across designs.

4. Label rebalancing for regression and classification

CircuitGCL’s supervised component is motivated by the mismatch between training and target label distributions. The paper formulates this through a change-of-measure relation between $V$ 6 and a balanced conditional distribution $V$ 7:

$V$ 8

For edge-level regression, the base model assumes standard MSE and Gaussian likelihood,

$V$ 9

The balanced MSE objective is written as

$A$ 0

Two practical instantiations are used. In the GMM-based analytical integration (GAI) variant,

$A$ 1

and

$A$ 2

In the batch-based Monte Carlo (BMC) variant,

$A$ 3

For node-level classification, CircuitGCL uses balanced softmax cross-entropy (bsmCE). The balanced conditional is modeled by a softmax,

$A$ 4

and the training-time distribution is adjusted by class priors,

$A$ 5

The bsmCE loss is the cross-entropy of this adjusted $A$ 6 with the ground-truth label, while inference uses the balanced softmax $A$ 7. The supervised objectives are therefore task-specific but derived from a shared distribution-alignment principle. A plausible implication is that CircuitGCL treats transfer not only as a representation problem but also as a statistical reweighting problem.

5. Tasks, metrics, and empirical behavior

CircuitGCL is evaluated on two downstream tasks with distinct target structures. For edge regression, the targets are coupling capacitances for candidate edges, with labels retained in a physical range exemplified by $A$ 8 in the experiments. For node classification, each net node is assigned one of five ground-capacitance categories, $A$ 9; category 2 is described as the largest middle bin, and evaluation excludes this majority bin for clearer minority-class comparison (Shen et al., 9 Jul 2025).

Task	Target	Metrics
Edge regression	Coupling capacitance for candidate edges	MAE, MSE, $E$ 0
Node classification	Ground capacitance category on net nodes	Accuracy, Precision, Recall, F1 score

The empirical results reported for zero-shot cross-design transfer are substantial. On edge regression, CircuitGCL is reported to improve $E$ 1 by $E$ 2 over prior state-of-the-art methods, with a specific result of $E$ 3 versus DLPL-Cap’s $E$ 4 on the largest design, corresponding to a relative improvement of $E$ 5. On a small digital test case, the GAI variant reduces MAE by $E$ 6 over DLPL-Cap. The BMC variant is reported to have larger absolute loss because of its normalization, but competitive MAE and $E$ 7, with examples including MAE $E$ 8 and $E$ 9 in the range $X \in \{0,1,2\}^{N \times 1}$ 0– $X \in \{0,1,2\}^{N \times 1}$ 1.

For node classification, CircuitGCL is reported to achieve Accuracy $X \in \{0,1,2\}^{N \times 1}$ 2 and F1 $X \in \{0,1,2\}^{N \times 1}$ 3 on one large design, described as a $X \in \{0,1,2\}^{N \times 1}$ 4 accuracy improvement over DLPL-Cap, and Accuracy $X \in \{0,1,2\}^{N \times 1}$ 5 with F1 $X \in \{0,1,2\}^{N \times 1}$ 6 on another design. On a challenging design it attains F1 $X \in \{0,1,2\}^{N \times 1}$ 7, reported as $X \in \{0,1,2\}^{N \times 1}$ 8 over DLPL-Cap. Across baselines, the paper states an F1-score gain of $X \in \{0,1,2\}^{N \times 1}$ 9. ParaGraph and CircuitGPS are described as showing poor scalability on large designs, with F1 below $f_{\phi}(\cdot)$ 0, whereas CircuitGCL maintains high F1.

The ablation studies attribute much of this behavior to RSM. The largest reported gains from adding representation scattering are $f_{\phi}(\cdot)$ 1 in $f_{\phi}(\cdot)$ 2 on the SRAM array and $f_{\phi}(\cdot)$ 3 in F1 on a large-scale design, with minimum gains of $f_{\phi}(\cdot)$ 4 and $f_{\phi}(\cdot)$ 5, respectively, and no reported performance degradation. The t-SNE visualizations are said to show uniform hyperspherical coverage with semantically meaningful clustering. Label rebalancing also contributes materially: bsmCE yields significant accuracy improvements across designs, particularly gains above $f_{\phi}(\cdot)$ 6 on large-scale designs, while bMSE improves performance in sparse regions of the continuous label space, including gains of $f_{\phi}(\cdot)$ 7– $f_{\phi}(\cdot)$ 8 in medium-low density regions.

6. Practical characteristics, limitations, and nomenclature

The implementation is reported in PyTorch Geometric, with subgraph batching through LinkNeighborLoader. Reported runtime settings include ClusterGCN $f_{\phi}(\cdot)$ 9, GraphSAGE $f_{\theta}(\cdot)$ 0 or $f_{\theta}(\cdot)$ 1, dropout $f_{\theta}(\cdot)$ 2, EMA decay $f_{\theta}(\cdot)$ 3, and $f_{\theta}(\cdot)$ 4 for bMSE. Hardware consists of a 40-core Intel Xeon server with 128 GB RAM and a single NVIDIA RTX 4090 (24 GB) per run (Shen et al., 9 Jul 2025).

The resource comparison against heavy positional encodings is part of the framework’s practical argument. On small to large datasets, DSPD is reported to require $f_{\theta}(\cdot)$ 5– $f_{\theta}(\cdot)$ 6 minutes of CPU time, up to $f_{\theta}(\cdot)$ 7 GB of memory, and MB-to-GB-scale disk storage, whereas CircuitGCL pretraining takes $f_{\theta}(\cdot)$ 8– $f_{\theta}(\cdot)$ 9 minutes of GPU time, $q_{\theta}(\cdot)$ 0– $q_{\theta}(\cdot)$ 1 GB of GPU memory, and approximately $q_{\theta}(\cdot)$ 2 MB of disk space. The stated conclusion is that CircuitGCL replaces heavy positional encodings with fast, parallel pretraining and scales better to large mixed-signal graphs.

Its limitations are also explicit. Performance depends on graph construction quality, so incorrect net, device, or pin parsing, or missing device types, can degrade transfer. Extreme label imbalance and unseen technologies or devices remain challenging, even though bMSE and bsmCE mitigate some of these effects. Proposed extensions include resistance and inductance prediction, crosstalk analysis, IR drop, and cross-technology transfer.

A separate point of clarification concerns nomenclature. In the provided literature, the string “CircuitGCL” is also used for a canonical lossless network that realizes a prescribed quadratic Lagrangian through LC fundamental loops coupled by GLC-links in the circuit-synthesis framework of "Circuit Synthesis based on Prescribed Lagrangian" (Figotin, 2020). That usage refers to a constructive mapping between quadratic Lagrangians and lossless electric circuits, not to graph contrastive learning. The two usages are technically unrelated. In current AMS parasitic-estimation context, CircuitGCL denotes the graph contrastive learning framework described above.