HGQ-LUT: Efficient LUT-Centric Inference

• HGQ-LUT is a lookup-table-centric inference method that transforms neural network operations into efficient table lookups and reductions.
• It employs fine-grained and hierarchical quantization along with hardware-guided training to optimize resource utilization across FPGA, CPU, and in-memory systems.
• Practical implementations demonstrate significant speedups, LUT reductions, and energy efficiency improvements in DNN and LLM applications.

HGQ-LUT denotes a class of lookup-table-centric inference methods in which quantization is made sufficiently fine-grained, hierarchical, or hardware-guided that deployment reduces to table lookups plus reductions instead of conventional multiply-accumulate pipelines. In its most explicit usage, HGQ-LUT is the LUT-aware training framework introduced in "HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference," which combines LUT-Dense and LUT-Conv layers with element-wise heterogeneous quantization, zero-bit pruning, and an end-to-end FPGA compilation flow (Sun et al., 24 Apr 2026). In related literature, the label is also used descriptively for broader constructions that share the same principle, including hierarchical nested-lattice quantization with small LUTs, FPGA tabulation of Kolmogorov-Arnold edge functions, group-wise hierarchical linear quantization for LLM LUT kernels, and in-DRAM per-group LUT generation for W4A4 inference (Kaplan et al., 19 May 2025, Hoang et al., 14 Dec 2025, Nie et al., 22 Oct 2025, Tian et al., 8 Jun 2026).

1. Terminology and scope

The label is not used uniformly across the literature. In the FPGA DNN setting, HGQ-LUT is a named framework built around LUT-aware training, HGQ quantizers, and automatic compilation to logic LUTs (Sun et al., 24 Apr 2026). In several adjacent works, however, the papers do not use the term explicitly; instead, later technical summaries use it to denote the broader idea of choosing quantization, grouping, and table organization so inference can be executed through LUT-native hardware paths (Kaplan et al., 19 May 2025, Hoang et al., 14 Dec 2025, Nie et al., 22 Oct 2025, Tian et al., 8 Jun 2026).

Usage	Representative formulation	Primary substrate
Explicit HGQ-LUT	LUT-Dense and LUT-Conv with HGQ quantizers	FPGA logic LUTs
Hierarchical nested-lattice quantization with LUT decoding	$M$-layer inner-product reconstruction from a small LUT	Cache-resident LUTs
Hardware-guided KAN tabulation	1D spline edge functions discretized into L-LUTs	FPGA logic LUTs
HLQ with LUT-based GEMM	$\hat W = \sum_{j=0}^{q-1} s_j b_j + z$	Edge CPU LUT kernels
PALUTE HGQ-LUT interpretation	Per-group W4A4 LUTs generated and queried in DRAM	M3D DRAM PIM

This breadth matters because a common misconception is to treat HGQ-LUT as a single, fixed algorithm. The literature instead contains a specific framework and a family resemblance: fine-grained or hierarchical quantization is coupled to LUT execution, and hardware costs are exposed during training or code construction rather than deferred to post hoc synthesis.

2. Core mathematical formulations

In the explicit FPGA framework, the central abstraction is the 1-input logical LUT, where “one input” refers to the logical signal and that signal is multi-bit in hardware. A LUT-Dense layer is defined as

$$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$

This is presented as a relaxation of a dense layer, and by reparameterizing intermediate activations,

$$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$

with

$$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$

the LUT formulation becomes equivalent to the reparameterized dense layer. LUT-Conv is obtained by preceding LUT-Dense with an im2col transform, so convolutional receptive fields are unfolded into vectors and processed with the same LUT machinery (Sun et al., 24 Apr 2026).

KANELÉ applies the same LUT-native idea to Kolmogorov-Arnold Networks. A KAN layer with input dimension $d_{\mathrm{in}}$ and output dimension $d_{\mathrm{out}}$ is a matrix of univariate edge functions,

$$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$

and edge activations are parameterized with B-spline bases on a fixed domain $[a,b]$. Because each $\phi_{q,p}$ is a learned one-dimensional function, it can be tabulated directly,

$\hat W = \sum_{j=0}^{q-1} s_j b_j + z$0

with optional interpolation at inference. This edge-based decomposition makes pruning structurally simple and makes FPGA inference a matter of L-LUT evaluation followed by pipelined summation (Hoang et al., 14 Dec 2025).

In hierarchical nested-lattice quantization for matrix multiplication, the LUT object is not a neural activation table but a codebook of inner products between low-rate lattice-code components. A rate-$\hat W = \sum_{j=0}^{q-1} s_j b_j + z$1 code is split into $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$2 layers of rate $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$3, replacing a single LUT of size $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$4 with a smaller LUT of size

$\hat W = \sum_{j=0}^{q-1} s_j b_j + z$5

while reconstructing inner products through

$\hat W = \sum_{j=0}^{q-1} s_j b_j + z$6

The formal purpose is to keep LUT-based inner-product decoding feasible at high quantization rates without materially increasing distortion (Kaplan et al., 19 May 2025).

For edge LLM inference on CPUs, ELUTQ introduces Hierarchical Linear Quantization, again with an explicitly linear decomposition:

$\hat W = \sum_{j=0}^{q-1} s_j b_j + z$7

Because the representation is linear in the binary planes $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$8, GEMM can be written as

$\hat W = \sum_{j=0}^{q-1} s_j b_j + z$9

so the runtime path becomes LUT lookups for activation–binary-pattern dot products plus scalar accumulations, eliminating dequantization overhead on the critical path (Nie et al., 22 Oct 2025).

3. Quantization, pruning, and resource-aware optimization

The defining training idea in HGQ-LUT is that quantization is not an afterthought but a differentiable, element-wise optimization variable coupled to a LUT-aware resource surrogate. Inputs use WRAP-mode quantization, outputs use SAT-mode quantization, and zero-bit support is native: if either the input or output element’s bit-width of a given L-LUT is set to zero, that L-LUT is pruned automatically. The training objective augments task loss with a LUT resource term,

$$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$0

where the per-L-LUT surrogate depends on input bit-width $$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$1, output bit-width $$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$2, and FPGA LUT primitive parameters. For $$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$3,

$$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$4

and empirically

$$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$5

A single scalar $$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$6 schedule is then used to trace an accuracy-resource Pareto frontier in one run (Sun et al., 24 Apr 2026).

RQP, or resource-oriented quantiser pruning, extends the HGQ line by making bit-widths themselves the optimization target at weight granularity and by replacing monotonic resource reduction with a direct jump to the target resource region. Its EBOPs proxy is

$$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$7

with LUT usage modeled as $$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$8. RQP introduces one-shot target-budget bit-width reallocation, spectral-constrained topology compensation, and bidirectional $$a_i^{(l)} = \sum_{j=1}^{N} \mathrm{L\textrm{-}LUT}_{i,j}\!\big(a_j^{(l-1)}\big).$$9 scheduling, so the search can move around the target budget instead of compressing irreversibly toward it. On jet substructure classification, this reduces search cost by up to $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$0 relative to monotonic HGQ workflows while keeping a competitive Pareto frontier (Li et al., 29 Jun 2026).

KANELÉ adopts quantization-aware training via Brevitas and inserts quantizers at the network input and after each layer so the training graph matches inference precision. Layer outputs are quantized as

$$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$1

with STE for gradients. Bit-widths are explored layer-wise from 1 to 8 bits, and the reported ablations show LUT use drops exponentially with bit-width while diminishing returns appear below 6 bits. Pruning exploits the additive independence of KAN edges through an $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$2-norm importance metric and an exponential warm-up threshold $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$3, so resource pressure is aligned with direct hardware savings in logic LUTs and FFs (Hoang et al., 14 Dec 2025).

ELUTQ places the optimization focus on HLQ parameter search and low-bit LLM deployment. In HLQ-GPTQ, group-wise scales and zero-points are optimized by a nearest-neighbor codebook selection followed by continuous updates of $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$4 and $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$5; an alternating least-squares variant is also described. Efficient finetuning then proceeds in two stages: a block-wise reconstruction phase minimizing

$$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$6

followed by end-to-end tuning of scales only. The result is a quantization format that remains orthogonal to existing PTQ or QAT pipelines while staying compatible with LUT execution (Nie et al., 22 Oct 2025).

4. Compilation flows and hardware realizations

The explicit HGQ-LUT framework is tightly integrated with HGQ2 and da4ml. During training, each L-LUT is represented by an MLP surrogate implemented with regular tensor operations, typically monolithic GEMMs or einsums. During compilation, the truth table for each L-LUT is generated by enumerating all possible input bit patterns, evaluating the trained surrogate, and applying output quantization. The compiled model is lowered to da4ml’s Distributed Arithmetic Instruction Set with a custom L-LUT instruction, then emitted as Verilog or VHDL. Bit-exact verification is performed with a DAIS interpreter and RTL-level checks through GHDL or Verilator, and hybrid models mixing L-LUT instructions with arithmetic instructions are supported natively (Sun et al., 24 Apr 2026).

KANELÉ provides a separate FPGA-oriented design flow for KANs. Training is followed by conversion of surviving edges to L-LUTs, enumeration of input state spaces, storage of integer truth tables in JSON, and generation of VHDL RTL for per-layer packages, LUT entities, adder trees, pipeline registers, and memory initialization files. The hardware mapping uses distributed ROM built from logic LUTs rather than BRAM or DSPs, with aggressive pipelining to sustain reported clocks of $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$7 to $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$8 MHz and initiation interval $$a_i'^{(l)} = \sum_{j=1}^{N} w_{ij}^{(l)} \,\phi^{(l-1)}\!\big(a_j'^{(l-1)}\big) + b_i^{(l)},$$9 (Hoang et al., 14 Dec 2025).

PALUTE relocates the LUT substrate from FPGA logic to Monolithic 3D DRAM. Its memory fabric uses a Vertical Bitline topology in which a bank comprises $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$0 MATs, each channel is a $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$1 array of banks, and the chip integrates a $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$2 array of channels. A near-memory LUT generator on a hybrid-bonded logic die materializes GEMM and unary-operator LUTs in three cycles at $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$3 MHz and writes them into a dedicated middle LUT region. Under the stated geometry and row-buffer bandwidth assumptions, the design reaches up to $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$4 simultaneous LUT reads, making group-wise HGQ-LUT-style inference a memory-system problem rather than a logic-synthesis problem (Tian et al., 8 Jun 2026).

Dedicated accelerator and CPU realizations show that the same abstraction also survives outside FPGA workflows. FIGLUT replaces FP-INT arithmetic with RAC units reading conflict-free FFLUT or half-size hFFLUT tables; with $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$5 and $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$6, the design is tuned to reduce arithmetic energy while keeping LUT fan-out manageable. ELUTQ, by contrast, targets ARM NEON-class CPUs, rearranging one-bit weight matrices offline, building activation-group LUTs at runtime, and using vectorized table-lookup instructions so inference proceeds through bit-serial LUT-based GEMM rather than dequantize-then-multiply kernels (Park et al., 10 Mar 2025, Nie et al., 22 Oct 2025).

5. Representative systems and reported performance

System	Representative reported result	Domain
HGQ-LUT	$$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$7 training speedup over NLA	FPGA LUT-aware training
KANELÉ	Up to $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$8 latency speedup and $$\mathrm{L\textrm{-}LUT}_{i,j}(x)=w_{ij}^{(l)}\phi^{(l-1)}(x)+\frac{b_i^{(l)}}{N},$$9 LUT reduction vs prior KAN-on-FPGA	LUT-native KAN inference
PALUTE	$d_{\mathrm{in}}$0 TPS at $d_{\mathrm{in}}$1 W	Edge LLM PIM
ELUTQ	Over $d_{\mathrm{in}}$2 tokens/s on Apple M2 for 2-bit LLaMA2-7B	CPU edge LLM
RQP	Up to $d_{\mathrm{in}}$3 reduction in search cost	FPGA quantiser pruning

Within the explicit FPGA DNN workflow, HGQ-LUT reports per-batch training time comparable to plain HGQ and a $d_{\mathrm{in}}$4 speedup over NLA. On HLF JSC, using two HGQ-LUT layers of dimensions 20 and 5, it reports the best accuracy-LUT Pareto frontier on both OpenML and CERNBox datasets, with a pronounced advantage in the low-LUT region. On TGC muon tracking, a hybrid architecture achieves the same accuracy as a plain HGQ baseline with $d_{\mathrm{in}}$5 lower latency and $d_{\mathrm{in}}$6 lower LUT utilization. On CEPC drift chamber cluster counting, under an embedded budget below $d_{\mathrm{in}}$7k LUTs, the reported implementation uses $d_{\mathrm{in}}$8 LUTs, $d_{\mathrm{in}}$9 DSP, $d_{\mathrm{out}}$0 BRAM, $d_{\mathrm{out}}$1 FFs, $d_{\mathrm{out}}$2 MHz $d_{\mathrm{out}}$3, latency $d_{\mathrm{out}}$4 cycles, and $d_{\mathrm{out}}$5 cycles (Sun et al., 24 Apr 2026).

KANELÉ emphasizes the case where the learned function itself is already decomposed into LUT-friendly univariate components. On Moons, Wine, and Dry Bean, the reported KANELÉ designs have latencies of $d_{\mathrm{out}}$6 to $d_{\mathrm{out}}$7 ns, $d_{\mathrm{out}}$8 of $d_{\mathrm{out}}$9 to $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$0 MHz, logic LUTs of $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$1 to $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$2 to $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$3, FFs of $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$4 to $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$5 to $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$6, and $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$7 BRAM and $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$8 DSP, against prior KAN-on-FPGA baselines with latencies $$(x_{l+1})_j = \sum_{i=1}^{d_l} \phi_{j,i}(x_{l,i}),$$9 to $[a,b]$0 to $[a,b]$1 ns and much larger resource footprints. On JSC CERNBox it reports $[a,b]$2 accuracy with $[a,b]$3 LUTs, $[a,b]$4 FFs, $[a,b]$5 MHz $[a,b]$6, $[a,b]$7 ns latency, and Area$[a,b]$8Delay $[a,b]$9; on JSC OpenML it reports $\phi_{q,p}$0 with $\phi_{q,p}$1 LUTs and $\phi_{q,p}$2 MHz $\phi_{q,p}$3; on MNIST it reaches $\phi_{q,p}$4 with $\phi_{q,p}$5 LUTs and $\phi_{q,p}$6 ns latency. On MLPerf Tiny ToyADMOS it reports AUC $\phi_{q,p}$7, $\phi_{q,p}$8 LUTs, $\phi_{q,p}$9 FFs, $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$00, throughput $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$01M inferences/s, latency $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$02s, and energy $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$03J/inference (Hoang et al., 14 Dec 2025).

RQP focuses on search efficiency rather than a new inference primitive, but its results are directly relevant to HGQ-LUT deployments because the resource proxy is the same LUT-facing EBOP model. Around a $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$04-EBOP target, standard HGQ requires up to $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$05k epochs and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$06 minutes to reach $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$07 accuracy at $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$08 EBOPs, whereas RQP uses $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$09k total epochs and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$10 minutes to reach $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$11 at $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$12 EBOPs. Post-implementation on a Xilinx Virtex Ultrascale+ xcvu13p-flga2577-2-e, representative RQP points include $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$13 LUTs at $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$14 MHz and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$15 ns, $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$16 LUTs at $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$17 MHz and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$18 ns, and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$19 LUTs at $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$20 MHz and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$21 ns (Li et al., 29 Jun 2026).

In LLM deployment, ELUTQ and PALUTE illustrate two different endpoints of the same design philosophy. ELUTQ reports that for LLaMA3-8B, HLQ reduces perplexity by about $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$22 at 3-bit and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$23 at 2-bit precision under post-training quantization, and that efficient finetuning further improves 2-bit performance within two hours. For 2-bit LLaMA2-7B on an Apple M2 chip with 4 threads and batch size $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$24, the system achieves over $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$25 tokens/s, and measured kernel latencies show essentially no added runtime overhead relative to uniform quantization inside LUT kernels. PALUTE reports $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$26 TPS end-to-end throughput at $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$27 W, corresponding to $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$28 TPS/W, with $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$29 energy efficiency over CHIME, $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$30 over FIGLUT, and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$31 area efficiency over PIMPAL under W4A4 across Qwen3-4B models (Nie et al., 22 Oct 2025, Tian et al., 8 Jun 2026).

FIGLUT provides the accelerator-side comparison point for weight-only FP-INT LUT GEMM. For the same 3-bit weight precision, it reports $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$32 higher TOPS/W and $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$33 lower perplexity than state-of-the-art accelerator designs; at matched perplexity, it reports $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$34 higher TOPS/W by performing $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$35-bit operations. The design also reports up to $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$36 energy-efficiency gains over FIGNA at Q2 and about $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$37 at Q3, showing that LUT execution can outperform integer-multiplier pipelines when the quantization format remains compatible with bit-serial table indexing (Park et al., 10 Mar 2025).

6. Limitations, misconceptions, and open directions

A first limitation is terminological. The acronym is explicit in the FPGA LUT-aware training paper, but several related papers state that they do not use the term explicitly and only match it “in spirit” or through a closest construct. A precise reading therefore distinguishes named HGQ-LUT from broader hardware-guided or hierarchical LUT-native quantization schemes rather than conflating them into one canonical algorithm (Kaplan et al., 19 May 2025, Hoang et al., 14 Dec 2025, Tian et al., 8 Jun 2026, Nie et al., 22 Oct 2025).

A second limitation is structural. In the explicit FPGA framework, 1-input L-LUTs are less expressive than high-fan-in LUTs, truth-table enumeration still grows as $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$38, backend LUT packing is vendor-specific when $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$39, and da4ml’s pipelining heuristics were not yet optimized, which is why global retiming was enabled in the reported flow. The same paper also notes fairness issues in prior reporting, including use of the test set for validation, omission of input clamping, unregistered top-level outputs with global retiming, and unseeded shuffling, indicating that post-P&R comparisons must be interpreted carefully (Sun et al., 24 Apr 2026).

KANELÉ highlights a different set of bottlenecks: approximation error versus LUT size, sensitivity to domain selection $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$40, degradation in accuracy and stability below 6 bits on many tasks, extra logic cost for interpolation, and growth of adder trees with fan-in. The paper therefore points to adaptive binning, mixed precision per layer or edge, partial reconfiguration, on-chip finetuning, and convolutional, temporal, or graph KANs as future directions (Hoang et al., 14 Dec 2025).

For LLM-oriented systems, capacity and memory-system effects dominate. PALUTE notes that at higher precision such as W8A8, per-group LUT entries grow exponentially, so grouping, half-table symmetry, and descriptor reuse become necessary just to contain capacity. ELUTQ notes that decode-stage GEMV remains more memory-bound than prefill-stage GEMM and that training is sensitive to learning rate. FIGLUT shows that LUT size grows as $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$41, fan-out sharing introduces overhead, and activation-dependent LUT regeneration can become a bottleneck if $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$42 is too large. These constraints suggest that successful HGQ-LUT deployments depend as much on address-space design, group granularity, and memory placement as on the quantizer itself (Tian et al., 8 Jun 2026, Nie et al., 22 Oct 2025, Park et al., 10 Mar 2025).

Finally, the resource surrogate itself is not universal. RQP explicitly notes that the empirical relation $\hat W = \sum_{j=0}^{q-1} s_j b_j + z$43 is model-specific and flow-specific, validated on xcvu13p with Vivado 2025.1 out-of-context place-and-route. This suggests that HGQ-LUT-style training remains portable in methodology but not calibration: deploying to other FPGA families, other synthesis flows, or non-FPGA substrates requires re-fitting the resource model even when the LUT-native computational principle remains unchanged (Li et al., 29 Jun 2026).