Pattern-Aware LUT Optimization

• Pattern-aware LUT optimization is a set of techniques that align LUT parameterizations with inherent data or hardware patterns to reduce size and enhance efficiency.
• It employs methods such as low-rank decompositions, complementary indexing, and symmetry reduction to overcome exponential scaling challenges in LUT designs.
• Applications span image processing, neural network acceleration, FPGA mapping, and low-bit inference, balancing efficiency trade-offs with high performance.

Searching arXiv for papers on pattern-aware LUT optimization and closely related LUT methods. Pattern-aware LUT optimization denotes a family of techniques that improve lookup-table representations by exploiting recurring structure in the target function, data distribution, or hardware realization. Across image enhancement, image restoration, LUT-based neural networks, FPGA technology mapping, and low-bit LLM inference, the central idea is consistent: replace dense or universal LUT parameterizations with formulations aligned to observed patterns, such as low-rank residuals, complementary indexing patterns, structured connectivity, repeated Boolean cofactors, symmetry in ternary arithmetic, or skewed distributions of practical functions (Zhao et al., 26 Feb 2026, Li et al., 2023, Lou et al., 14 Jan 2026, Calvino et al., 2024, Geens et al., 28 Apr 2026). This suggests that the term refers not to a single algorithm, but to a general optimization principle for making LUTs smaller, faster, more interpretable, or more accurate by matching them to the structure actually present in the workload.

1. Formal foundations and recurring bottlenecks

A LUT stores a discretized mapping from an input domain to precomputed outputs. In image enhancement, a 3D LUT discretizes the RGB cube into a grid of size $G$ and defines a mapping by trilinear interpolation,

$$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$

with the commonly used grid size $G = 33$ (Zhao et al., 26 Feb 2026). In LUT-based DNNs and FPGA inference, the governing scaling law is exponential: a neuron with $\beta$-bit activations and fan-in $F$ requires a truth table of size $S(\beta F)=2^{\beta F}$, and an $m$-input logical LUT has $2^m$ entries (Lou et al., 14 Jan 2026, Andronic et al., 14 Jan 2025). In image restoration, a single sampled LUT has storage

$$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$

so enlarging indexing capacity increases storage exponentially in $n$ (Li et al., 2023).

Pattern-aware methods target precisely these scaling barriers. Some reduce the intrinsic dimensionality of the stored function, as in low-rank tensor decompositions for color cubes or SVD decompositions of pairwise color mappings (Zhao et al., 26 Feb 2026, Kim et al., 22 Aug 2025). Others keep the table interface fixed but optimize what is indexed, such as complementary spatial patterns, learned sparse connectivity, or “don’t care” truth-table entries (Li et al., 2023, Lou et al., 17 Mar 2025, Lou et al., 17 Mar 2025). In hardware, the same principle appears as symmetry reduction, reuse of repeated partial sums, or exploiting the fact that only a tiny subset of all Boolean functions occurs in real mapped netlists (Geens et al., 28 Apr 2026, Yang et al., 20 Mar 2025).

A second recurring bottleneck is that LUT efficiency depends not only on table size but also on how the table is applied. Many recent methods therefore preserve constant-time lookup semantics while shifting complexity into offline generation, per-image reconstruction, or per-tile precomputation. This pattern appears in low-rank residual reconstruction for 3D LUTs, on-the-fly precompute tables for FP-INT GEMM, and dynamic pattern scheduling in fixed-latency decoders (Zhao et al., 26 Feb 2026, Park et al., 10 Mar 2025, Condo, 2021).

2. Image-domain LUTs: color structure, spatial context, and decomposition

In image enhancement and style transfer, pattern-aware LUT optimization is primarily about matching color transformations to structured variation in the RGB cube or to spatial context. LoR-LUT formulates an image-specific LUT as

$$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$0

with the residual parameterized by a CP-style decomposition

$$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$1

This replaces dense fusion with low-rank residual corrections that act as separable “color brushes” along the R/G/B axes. The parameter count for the residual is $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$2 instead of $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$3, so at $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$4 and $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$5 the correction factors use $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$6 parameters rather than $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$7 for a dense LUT. On MIT-Adobe FiveK, LoR-LUT reports, for example, PSNR $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$8 dB, SSIM $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$9, LPIPS $G = 33$0 at $G = 33$1 and PSNR $G = 33$2 dB, SSIM $G = 33$3, LPIPS $G = 33$4 at $G = 33$5, with a residual-only $G = 33$6 model of $G = 33$7M parameters, $G = 33$8 MB, and 4K latency $G = 33$9 ms on NVIDIA T4 (Zhao et al., 26 Feb 2026).

SA-LUT extends the same logic from global color structure to spatial patterns. It introduces a 4D LUT with an additional context dimension and a per-pixel context map $\beta$0 produced by content-style cross-attention. The fused LUT is

$\beta$1

and the rendered output is obtained by quadrilinear interpolation,

$\beta$2

The additional dimension lets identical colors be treated differently in different semantic or spatial regions. On the PST50 benchmark, SA-LUT reports LPIPS $\beta$3, PSNR $\beta$4, SSIM $\beta$5, H-Corr $\beta$6, and a $\beta$7 reduction in LPIPS compared to 3D LUT approaches, while maintaining real-time video stylization at 16 FPS and 4K at over 16 FPS (Gong et al., 16 Jun 2025).

SVDLUT addresses a different redundancy: underuse of 3D spatial-aware LUT entries and bilateral-grid vertices. It decomposes each 3D LUT channel into three 2D LUTs,

$\beta$8

and further factorizes each 2D LUT by SVD, $\beta$9. The same paper decomposes 3D bilateral grids into 2D grids and fuses slicing with LUT transform to remove high-resolution intermediate tensors. With $F$0, $F$1, and $F$2, the reported model has $F$3K parameters and 4K runtime $F$4 ms, compared with $F$5K parameters and $F$6 ms for SABLUT, while preserving or improving PSNR and $F$7 on FiveK and PPR10K (Kim et al., 22 Aug 2025).

MuLUT generalizes the image-domain idea from single tables to a “network of LUTs.” It uses complementary indexing patterns such as S, D, and Y, hierarchical re-indexing across cascaded stages, and channel indexing for cross-channel interaction. The key claim is that total size becomes linear in indexing capacity rather than exponential, and the reported gains include up to $F$8 dB PSNR for super-resolution, up to $F$9 dB PSNR for grayscale denoising, and $S(\beta F)=2^{\beta F}$0 less energy cost compared with lightweight deep neural networks (Li et al., 2023).

3. LUT-based neural networks: structured connectivity, decomposition, and trainability

In LUT-based DNNs, pattern-aware optimization is driven by the conflict between representational capacity and the exponential cost of wide truth tables. PolyLUT addresses this by replacing linear neurons with multivariate polynomial neurons,

$S(\beta F)=2^{\beta F}$1

while enforcing low fan-in through the hardware-aware group regularizer

$S(\beta F)=2^{\beta F}$2

After dense training, only the top-$S(\beta F)=2^{\beta F}$3 inputs per neuron are kept. On jet tagging, a 2-layer polynomial network with $S(\beta F)=2^{\beta F}$4 reaches $S(\beta F)=2^{\beta F}$5 accuracy versus $S(\beta F)=2^{\beta F}$6 for a 4-layer linear network, with $S(\beta F)=2^{\beta F}$7 latency reduction and $S(\beta F)=2^{\beta F}$8 area reduction; the standard deviation of test accuracy across seeds also drops from $S(\beta F)=2^{\beta F}$9 under random pruning to $m$0 with structured pruning (Andronic et al., 14 Jan 2025).

PolyLUT-Add and SparseLUT continue this line by making patterns explicit either in architecture or connectivity. PolyLUT-Add factorizes a wide-input neuron into $m$1 sub-neurons of fan-in $m$2 plus an Adder-layer, changing the cost from monolithic $m$3 to

$m$4

Across MNIST HDR, JSC-XL, and JSC-M Lite, it reports LUT reductions of $m$5–$m$6 and latency reductions of $m$7–$m$8 at comparable accuracy (Lou et al., 2024). SparseLUT keeps the deployed LUT sizes unchanged but optimizes which inputs each LUT neuron selects. It uses masked parameters with

$m$9

a non-greedy prune/regrow schedule, and exact per-neuron fan-in enforcement in fine-tuning. The reported gains are up to $2^m$0 on MNIST and $2^m$1 on Jet Substructure Classification, with no hardware overhead and no latency penalty (Lou et al., 17 Mar 2025).

NeuraLUT-Assemble turns wide neurons into trees of smaller LUT-based sub-networks with mixed precision and skip-connections across entire LUT structures. The cost model is governed by per-node terms of the form $2^m$2, so pattern-aware grouping and mixed precision determine the area–delay product. The framework reports up to $2^m$3 reduction in the area-delay product compared to the state of the art at the time of publication, including a $2^m$4 ADP reduction versus NeuraLUT on MNIST and a $2^m$5 reduction versus NeuraLUT on one jet-classification setting (Andronic et al., 1 Apr 2025).

Two further developments broaden the scope. ReducedLUT injects “don’t care” values into unobserved LUT entries so that sub-tables become more self-similar under right shifts and biasing. This achieves up to $2^m$6 reduction in Physical LUT utilization with test accuracy drop no more than $2^m$7 accuracy points (Cassidy et al., 2024). HGQ-LUT, by contrast, focuses on trainability and end-to-end workflow: it uses 1-input logical LUTs, heterogeneous quantization with zero-bit pruning, and an EBOPs-based resource surrogate,

$2^m$8

to obtain state-of-the-art hardware efficiency while accelerating training by over $2^m$9 times, with an overall speedup measured at $$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$0 in HLF jet substructure classification (Sun et al., 24 Apr 2026).

4. Low-bit and ternary accelerators: symmetry, sparsity, and LUT-centric GEMM

For ternary and low-bit LLM inference, pattern-aware LUT optimization is driven by the algebraic regularities of low-cardinality weights. In the hardware-generator study for 1.58-bit LLM inference, group-based LUTs precompute

$$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$1

for ternary weight groups. A full LUT has $$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$2 entries, but symmetry reduction stores only

$$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$3

with an additional 1-bit symmetry flag controlling sign inversion. Combined with redundancy elimination and sparsity pruning, this yields a bound

$$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$4

and for $$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$5 the structured reductions cut adders by up to $$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$6 relative to a naive tree. The same work shows that the optimal architecture is governed by the activation data type: FP16 favors larger $$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$7 and wider fetch reuse, whereas INT8 pushes the optimum toward $$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$8 or small $$S_{\mathrm{single}} = \big(2^{8-q} + 1\big)^n \times m \ \mathrm{bytes},$$9. At 32×32 FP16, the LUT architecture with optimal $n$0 reduces area by $n$1 versus a dequantize-and-multiply baseline and by $n$2 versus a sign-flip multiplier baseline (Geens et al., 28 Apr 2026).

TENET pushes the ternary pattern-aware idea further by combining symmetry, sparsity, and mixed precision. Its Sparse Ternary LUT core maps each 2-element ternary group to three compact indices: GIdx for all-zero groups, DIdx for one of four dense precomputed partial products, and SIdx for sign mirroring. It also introduces Dynamic Activation N:M Sparsity and a LUT-based 64B:80B ternary weight decompression module. At the system level, these mechanisms are integrated with Linear-Projection-aware Sparse Attention. The reported end-to-end gains are $n$3 and $n$4 energy efficiency over A100 GPU for FPGA and ASIC, respectively, and a $n$5 average speedup in end-to-end inference latency for TENET-ASIC (Huang et al., 17 Sep 2025).

FIGLUT addresses FP-INT GEMM with a different pattern vocabulary: deterministic lookups keyed by weight patterns, conflict-free flip-flop LUT memory, and a half-size LUT with sign decoding,

$n$6

The half-size hFFLUT halves LUT storage and power, while on-the-fly LUT generation amortizes signed-sum construction over multiple read-accumulate units. For the same 3-bit weight precision, FIGLUT reports $n$7 higher TOPS/W and $n$8 lower perplexity than state-of-the-art accelerator designs; at the same perplexity, it achieves $n$9 higher TOPS/W by performing 2.4-bit operations (Park et al., 10 Mar 2025).

ELUTQ shows that pattern-awareness can also be encoded into the quantization format itself. Its Hierarchical Linear Quantization represents a weight as

$$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$00

so codepoints can be concentrated near the dense parts of the weight distribution without changing the bit-serial LUT-GEMM structure. On LLaMA3-8B, HLQ reduces WikiText-2 perplexity from $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$01 to $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$02 at 3-bit under GPTQ, and from $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$03 to $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$04 at 2-bit, with further 2-bit improvement to $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$05 under efficient finetuning. The same framework reports over $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$06 tokens/s for 2-bit LLaMA2-7B on an Apple M2 chip with 4 threads and batch size $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$07 (Nie et al., 22 Oct 2025).

5. Logic synthesis and FPGA mapping: recurring Boolean patterns and practical functions

In FPGA mapping, pattern-aware LUT optimization means exploiting repeated Boolean structure rather than treating all cuts or all truth tables as equally likely. Practical Ashenhurst–Curtis decomposition is the clearest functional example. Given a support partition $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$08, the function is expressed as

$$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$09

and the key statistic is the decomposition degree

$$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$10

the number of distinct column patterns in the Ashenhurst matrix. A two-level decomposition exists when $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$11 and $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$12. By recognizing repeated column patterns on the fly during cut enumeration, the method improves delay-driven LUT mapping with an average delay improvement of $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$13 and area reduction of $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$14, and improves 4 of the best delay results in the EPFL synthesis competition without employing design-space exploration techniques (Calvino et al., 2024).

FuseMap exploits a different structural prior: some ASIC-standard-cell packings induce gate-level motifs that map better into FPGA LUTs. It uses multi-armed bandits to select sampled libraries, then runs ASIC mapping before LUT mapping. The reward can optimize LUT count, delay, or area–delay product, for example

$$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$15

Across 24 ASAP7 designs, FuseMap improves LUT size in 20 of 24 designs, with average LUT reduction $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$16, delay improvement $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$17, and ADP improvement $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$18; across 161 designs, the average ADP improvement remains $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$19 (Yu, 15 Jul 2025).

DSLUT replaces the universal LUT with a domain-specific asymmetric LUT-like block targeted to “practical functions” mined from benchmarks. The motivating observation is that only 3881 out of more than $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$20 NPN classes of 6-input functions occur in mapped netlists of VTR8 and Koios benchmarks, and the top 20 6-input functions account for 80% of $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$21. DSLUT preserves the MUX tree but wires fewer SRAM bits to its leaves according to an optimized bit assignment. The resulting DSLUT6 uses 26 SRAM bits and, after ABC synthesis, reduces the number of levels by $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$22 at a cost of $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$23 area overhead compared to LUT5; after full VTR flow, it provides performance improvement by $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$24 over LUT5, close to $$y = \sum_{i=0}^1 \sum_{j=0}^1 \sum_{k=0}^1 w_{ijk} \cdot L[x_i, y_j, z_k],$$25 of LUT6 over LUT5, with less area overhead (Yang et al., 20 Mar 2025).

6. Common principles, limitations, and research trajectory

Despite the diversity of applications, several design principles recur. First, pattern-aware methods typically trade universal expressivity for alignment with the empirical structure of the workload: low-rank color corrections instead of dense 3D LUTs, complementary spatial patterns instead of monolithic receptive fields, learned sparse connectivity instead of random sparsity, symmetry-reduced ternary tables instead of full base-3 enumeration, and practical-function coverage instead of full Boolean universality (Zhao et al., 26 Feb 2026, Li et al., 2023, Lou et al., 17 Mar 2025, Geens et al., 28 Apr 2026, Yang et al., 20 Mar 2025). Second, they often preserve the lookup interface itself—trilinear interpolation, quadrilinear interpolation, truth-table evaluation, or bit-serial LUT reads—while moving optimization into factorization, indexing, scheduling, or table generation.

A common misconception is that pattern-aware optimization always means “more adaptive” LUTs. In fact, some methods increase adaptivity by adding spatial or semantic context, as in SA-LUT or MuLUT, whereas others reduce the hypothesis class to gain regularity, as in DSLUT or ReducedLUT. Another misconception is that LUT compression necessarily preserves all desirable constraints. LoR-LUT reports that monotonicity is not explicitly enforced along RGB axes in reported experiments; SA-LUT notes that under/overexposed content can break cross-attention correspondences and that temporal consistency is not explicitly optimized; ternary accelerator studies report that LUT benefits diminish for small integer activations because readout costs rival adder cost; SparseLUT still uses random regrowth; and DSLUT remains domain-specific by construction (Zhao et al., 26 Feb 2026, Gong et al., 16 Jun 2025, Geens et al., 28 Apr 2026, Lou et al., 17 Mar 2025, Yang et al., 20 Mar 2025).

The research trajectory indicated by these works is toward tighter co-design among statistics, architecture, and deployment substrate. Several papers already point in that direction: LoR-LUT proposes integration with spatial modules; SA-LUT motivates stronger semantic alignment and temporal consistency; HGQ-LUT couples bit-width learning to an explicit LUT surrogate; ternary accelerator work emphasizes datatype-aware architecture search; and FuseMap suggests richer pattern encodings beyond library-subset selection (Zhao et al., 26 Feb 2026, Gong et al., 16 Jun 2025, Sun et al., 24 Apr 2026, Geens et al., 28 Apr 2026, Yu, 15 Jul 2025). This suggests that future pattern-aware LUT optimization will be increasingly end-to-end: patterns will not only be exploited after discovery, but learned, encoded, and scheduled jointly with the hardware or interpolation mechanism that executes them.