Multi-Input Lookup Table Protocol

Updated 7 July 2026

Multi-input lookup table protocols transform structured inputs into precomputed indices, reducing online computation in neural, privacy-preserving, quantum, and FPGA designs.
They combine offline preprocessing—via centroid learning, bit-level decomposition, or secret sharing—with fast online lookup to replace repeated arithmetic calculations.
Optimized implementations balance memory, latency, and fidelity tradeoffs, achieving significant improvements in speed, model size, and energy efficiency across diverse applications.

Searching arXiv for papers relevant to multi-input lookup table protocols across ML, privacy-preserving computation, quantum lookup architectures, and FPGA LUT mapping. In the cited literature, a multi-input lookup table protocol is not a single standardized construction but a recurring computational pattern: multiple input components are transformed into an address, index, centroid identifier, or routing configuration, and a precomputed value is retrieved instead of recomputing the target function online. This pattern appears in learned neural inference systems that replace linear arithmetic with centroid lookup, in privacy-preserving machine learning protocols that retrieve secret-shared nonlinear values, in fault-tolerant quantum circuits that implement $k$ -bit addressable data access, in FPGA technology mapping where Boolean networks are covered by $k$ -input LUTs, and in multiplier-less neural inference schemes that partition bit-level or spatial inputs into table addresses (Tang et al., 2023, Saleem et al., 2024, Häner et al., 2022, Zhu et al., 2024, Yu, 15 Jul 2025, Lam et al., 2022, Wu, 2019).

1. Conceptual scope and recurring structure

Across these formulations, lookup-table evaluation typically separates an offline or preprocessing stage from an online execution stage. In LUT-NN, representative input patterns are learned as centroids and operator outputs for those centroids are precomputed into tables; in Hawk and Tabula, tables are generated offline and queried online under additive secret sharing; in quantum lookup circuits, data strings $d_0,\dots,d_{K-1}$ specify a table function $f:\{0,1\}^k\to\{0,1\}^m$ that is later queried by an address register; and in TableNet, affine layers are decomposed into table evaluations plus additions and shifts (Tang et al., 2023, Saleem et al., 2024, Lam et al., 2022, Häner et al., 2022, Wu, 2019).

A concise way to compare these usages is to distinguish what counts as the “input,” what is precomputed, and what the lookup returns.

Domain	Multi-input object	Retrieved result
DNN approximation	sub-vectors or packed token groups	precomputed operator contributions
PPML	secret-shared nonlinear input or noisy masked key	secret shares of $f(x)$
Quantum lookup	$k$ -bit address register	$m$ -bit data word
FPGA mapping	Boolean support of up to $k$ inputs	LUT-implementable logic function
Multiplier-less NN inference	bit chunks, bitplanes, or spatial patches	partial affine output

This suggests that “multi-input” has field-specific meanings. In neural approximation, it usually denotes structured high-dimensional inputs decomposed into sub-vectors or groups. In cryptography, it refers either to a secret-shared function argument or to protocol variants for handling functions that depend on several coordinates. In quantum computing, it denotes explicit address width $k$ . In FPGA design, it refers to the bounded fan-in of a physical LUT, typically 4 to 6 inputs (Tang et al., 2023, Saleem et al., 2024, Zhu et al., 2024, Yu, 15 Jul 2025).

2. Address formation, decomposition, and retrieval semantics

The central design problem is how to turn a structured input into a compact lookup address without losing too much fidelity, security, or implementability. LUT-NN adopts a product-quantization-style decomposition in which an input vector $a\in\mathbb{R}^D$ is split into $k$ 0 sub-vectors of length $k$ 1, with $k$ 2, and each sub-vector $k$ 3 is assigned to a centroid from a codebook $k$ 4. The encoding is nearest-centroid assignment,

$k$ 5

and the full multiplication is approximated by

$k$ 6

where $k$ 7 stores the precomputed dot products between centroids and weight sub-vectors. The paper emphasizes that with $k$ 8 centroids per codebook and $k$ 9 codebooks, the representation capacity is $d_0,\dots,d_{K-1}$ 0, while the memory cost is only $d_0,\dots,d_{K-1}$ 1 (Tang et al., 2023).

TableNet uses a more explicit bit-level decomposition. If the input set $d_0,\dots,d_{K-1}$ 2 needs $d_0,\dots,d_{K-1}$ 3 bits and the output set $d_0,\dots,d_{K-1}$ 4 needs $d_0,\dots,d_{K-1}$ 5 bits, a direct table requires $d_0,\dots,d_{K-1}$ 6 bits. To control the exponential growth, the input bits are partitioned into $d_0,\dots,d_{K-1}$ 7 chunks with $d_0,\dots,d_{K-1}$ 8; each chunk indexes its own LUT of size $d_0,\dots,d_{K-1}$ 9 bits, and partial outputs are summed. The same principle is applied to affine maps $f:\{0,1\}^k\to\{0,1\}^m$ 0, fixed-point bitplanes, floating-point mantissa/exponent decomposition, convolutional patches, signed numbers, and stochastic rounding, so that multiple input fragments jointly determine one or more LUT queries whose outputs are recombined additively (Wu, 2019).

Vec-LUT changes the granularity of the address rather than the approximation model. For mixed-precision GEMM $f:\{0,1\}^k\to\{0,1\}^m$ 1, with $f:\{0,1\}^k\to\{0,1\}^m$ 2, $f:\{0,1\}^k\to\{0,1\}^m$ 3, and grouped weights of size $f:\{0,1\}^k\to\{0,1\}^m$ 4, the unified LUT has shape

$f:\{0,1\}^k\to\{0,1\}^m$ 5

Each packed weight index $f:\{0,1\}^k\to\{0,1\}^m$ 6 addresses a vector of $f:\{0,1\}^k\to\{0,1\}^m$ 7 precomputed results, yielding the $f:\{0,1\}^k\to\{0,1\}^m$ 8 rule

$f:\{0,1\}^k\to\{0,1\}^m$ 9

Here the multi-input character arises from grouping $f(x)$ 0 ternary weights into a single decimal index and retrieving a token-parallel vector rather than a scalar (Li et al., 6 Dec 2025).

Quantum lookup protocols make address semantics explicit. The classical table function $f(x)$ 1 is implemented reversibly as

$f(x)$ 2

The unified quantum architecture similarly realizes

$f(x)$ 3

but parameterizes the routing and retrieval structure through memory partition size $f(x)$ 4 and CNOT-subtree size $f(x)$ 5, so the address is consumed by a hierarchical routing network rather than by a classical table index alone (Häner et al., 2022, Zhu et al., 2024).

3. Learned and approximate protocols for neural inference

In neural inference, the multi-input lookup-table protocol is principally a strategy for replacing arithmetic with indexed retrieval while preserving task accuracy. LUT-NN is described as the first system to empower inference by table lookup, and its central claim is that prior PQ-style approximations fail on deep networks because they optimize quantization distance rather than end-task loss. Its answer is differentiable centroid learning through backpropagation, with three explicit approximation controls: soft-PQ for differentiable centroid assignment, learned temperature for layer-specific softmax sharpness, and quantization-aware training for scalar-quantized lookup tables, typically INT8 (Tang et al., 2023).

The training-time relaxation replaces the non-differentiable $f(x)$ 6 with

$f(x)$ 7

and uses a straight-through-style formulation so that the forward pass matches hard inference behavior while the backward pass allows gradients to flow to centroids. The paper states that centroids are initialized with k-means from a sampled training subset, and that a separate temperature is learned per layer because approximation error compounds across many layers (Tang et al., 2023).

At inference, the protocol reduces to two stages: closest centroid search and table read plus accumulation. The hardware-aware aspect is not incidental. LUT-NN introduces centroid-stationary computation, intra-codebook parallelism, SIMD shuffle-based table lookup using pshfb on x86 and tbl on ARM, and mixed-precision accumulation that starts in INT16 and widens to INT32. On 128-bit SIMD, the shuffle-based design allows 16 lookups simultaneously. Reported savings include FLOPs reduction $f(x)$ 8 to $f(x)$ 9, model size reduction $k$ 0 to $k$ 1, latency reduction $k$ 2 to $k$ 3, memory reduction $k$ 4 to $k$ 5, and power reduction $k$ 6 to $k$ 7, while accuracy improves by $k$ 8 to $k$ 9 over directly applying Maddness and remains close to original models (Tang et al., 2023).

Vec-LUT addresses a different bottleneck: existing scalar LUT kernels underutilize memory bandwidth during parallel inference. The paper identifies the failure mode as the scalar $m$ 0 paradigm, in which each token builds a separate LUT and performs separate non-contiguous table accesses. Vec-LUT instead constructs a unified LUT across all $m$ 1 tokens and performs a single $m$ 2 lookup per index. The associated implementation includes Vector LUT-Centric Tensor Layout, Cache-Aware Streamed Lookup, INT16-INT32 hierarchical accumulation, and topological precomputing that reduces operations from $m$ 3 to $m$ 4, giving a speedup of $m$ 5 (Li et al., 6 Dec 2025).

The paper reports that memory bandwidth utilization in parallel inference can drop to $m$ 6 under scalar LUT execution. With vector LUT, lookup time becomes marginal in the reported breakdown for HF BitNet 3B prefilling: Precompute $m$ 7, Accumulate $m$ 8, Lookup $m$ 9, Others $k$ 0. End-to-end gains reach up to $k$ 1, and on AWS Graviton 3 the I2 configuration achieves 273.5 tokens/s, including 152.6 tokens/s prefilling and 120.9 tokens/s decoding (Li et al., 6 Dec 2025).

TableNet represents an earlier multiplier-less formulation. Rather than learning centroids, it decomposes trained inference into LUTs plus addition and bit-shifts, targeting dense layers and convolutions. The tradeoff is structural: larger LUTs reduce arithmetic, while smaller LUTs require more partitioning and therefore more LUT evaluations and additions. The paper emphasizes that similar performance can be obtained with a comparable memory footprint as a full precision deep neural network, but without the use of any multipliers (Wu, 2019).

4. Secure and privacy-preserving lookup protocols

In privacy-preserving machine learning, the lookup-table protocol is used primarily for nonlinear functions, because linear algebra under additive secret sharing is comparatively efficient while activations such as $k$ 2, $k$ 3, $k$ 4, and $k$ 5 are expensive under garbled circuits or polynomial approximations. Tabula and Hawk both replace those nonlinear subroutines with secure lookup tables, but they make different security-efficiency tradeoffs (Lam et al., 2022, Saleem et al., 2024).

Tabula is a secure inference protocol for nonlinear activations in the two-party semi-honest setting. Its key observation is that aggressive quantization makes the activation domain small enough to tabulate. In preprocessing, for each nonlinear activation call, a quantization scale $k$ 6 is chosen, a fresh secret $k$ 7 is generated and additively shared, and a secure lookup table $k$ 8 is initialized so that

$k$ 9

Online execution consists of secure truncation, revealing only the masked index $k$ 0, performing the lookup, and rescaling (Lam et al., 2022).

The online communication cost is stated as twice the field bitlength because the parties exchange shares of one masked field element. With a 64-bit field, this is 128 bits, or 16 bytes per activation. The paper reports that for a single ReLU, Tabula uses between $k$ 1- $k$ 2 less communication than garbled circuits in the abstract, and the detailed comparisons list 2.17 KB, 1.1 KB, and 0.562 KB for 32-bit, 16-bit, and 8-bit garbled circuits versus 16 B for Tabula. End-to-end, Tabula reduces inference communication by up to $k$ 3 and achieves up to $k$ 4 speedup, while focusing explicitly on online efficiency rather than preprocessing improvements (Lam et al., 2022).

Hawk extends secure lookup tables into privacy-preserving training and evaluation in a two-server model with non-colluding servers $k$ 5, using additive secret sharing over $k$ 6: $k$ 7 Its two protocols are $k$ 8, a one-time table-use protocol that is leakage-free or perfectly secure in the semi-honest model, and $k$ 9, a reusable-table protocol that leaks a privacy-preserving access pattern (Saleem et al., 2024).

HawkSingle uses fresh table-specific masks $a\in\mathbb{R}^D$ 0, random table permutations, and one-round online lookup. HawkMulti introduces elliptic-curve-based deterministic key derivation and a share-conversion subprotocol from $a\in\mathbb{R}^D$ 1 to $a\in\mathbb{R}^D$ 2, then perturbs the input by geometric noise,

$a\in\mathbb{R}^D$ 3

to obtain access-pattern leakage that satisfies local $a\in\mathbb{R}^D$ 4- $a\in\mathbb{R}^D$ 5-privacy with $a\in\mathbb{R}^D$ 6. The leakage is the pseudorandom lookup key

$a\in\mathbb{R}^D$ 7

which the paper interprets as essentially a histogram of accesses rather than raw plaintext values (Saleem et al., 2024).

The distinction between single-input and multi-input nonlinearities is especially visible in Hawk’s treatment of $a\in\mathbb{R}^D$ 8. Instead of a single huge multivariate table, Hawk uses two univariate tables—one for $a\in\mathbb{R}^D$ 9 and one for $k$ 00, where $k$ 01—and then multiplies. This is the paper’s explicit method for handling a multi-input function without exponential-size multivariate LUTs (Saleem et al., 2024). A common misunderstanding is that secure lookup tables eliminate all tradeoffs relative to garbled circuits; the literature instead shows a layered set of tradeoffs involving offline storage, number of rounds, leakage model, and quantization precision (Lam et al., 2022, Saleem et al., 2024).

5. Quantum multi-input lookup architectures

In quantum computing, the multi-input lookup-table protocol is a reversible data-access primitive whose inputs are address qubits and whose outputs are data qubits. The 2022 lattice-surgery work studies a classical table function $k$ 02 under fault-tolerant surface-code constraints on a 2D grid. Its lookup operation is

$k$ 03

with a controlled version that applies the lookup only when a control qubit is active. The logical construction is the unary-iterate lookup of Babbush et al., reorganized around surface-code primitives such as multi-target CNOT, AND, AND $k$ 04, CCiX, delayed-choice CZ, remote ZZ and XZ measurements, cat-state fanout, and switch-board routing (Häner et al., 2022).

This construction gives exact resource formulas. For uncontrolled lookup, the number of AND gates is $k$ 05 for $k$ 06, and because each AND costs four $k$ 07 states, the unary-iterate table lookup consumes

$k$ 08

The paper then derives logical-depth recurrences and 2D layout qubit counts, and introduces the zipper construction, which runs two lookup branches in parallel to trade more qubits for less critical depth (Häner et al., 2022).

The later unified architecture generalizes the landscape substantially. It implements quantum access to arbitrary classical data with two parameters: $k$ 09, the partition size of memory, and $k$ 10, the size of the CNOT subtree within a partition, with

$k$ 11

The architecture has three stages: address setting via linear routers and a CSWAP tree, memory querying within partitions, and retrieval by a final CSWAP tree (Zhu et al., 2024).

The main theorem states that for $k$ 12 memory locations,

$k$ 13

with an explicit infidelity expression that separates long-range gate error, SWAP error, idling error, CNOT error, CCNOT error, and CSWAP error. A highlighted regime is

$k$ 14

which yields

$k$ 15

The paper identifies this as simultaneous sublinear scaling in infidelity, $k$ 16-count, and qubit count (Zhu et al., 2024).

For multi-bit readout with word size $k$ 17, the unified architecture offers parallel and sequential schemes. Parallel multi-bit readout makes $k$ 18 copies of the single-bit structure, with resource costs that scale with $k$ 19. Sequential multi-bit readout reuses the routed signal and repeats Stage III $k$ 20 times, giving better $k$ 21-efficiency but extra idling error, specifically $k$ 22. The paper positions these as tunable tradeoffs rather than universally superior alternatives (Zhu et al., 2024). This suggests that, in the quantum setting, “protocol” refers as much to routing architecture and fault-tolerant layout as to lookup semantics.

6. Logic synthesis, hardware mapping, and cross-cutting tradeoffs

In FPGA design, the phrase LUT refers to a physical or logical primitive rather than to a stored table queried at runtime. FuseMap nevertheless belongs to the same conceptual family because it is concerned with how a Boolean network is reshaped so that multi-input LUT covering becomes more effective. An FPGA LUT is described as a flexible digital memory structure that can implement any logic function of a limited number of inputs, typically 4 to 6 inputs. FuseMap uses an ASIC technology mapping step as a controllable pre-processing stage so that the resulting netlist is structurally more favorable for subsequent multi-input LUT packing (Yu, 15 Jul 2025).

The central claim is negative before it is positive: naively chaining ASIC mapping then LUT mapping is usually worse than vanilla LUT mapping, and motivating examples report LUT-count increases of about $k$ 23 to $k$ 24 in a vanilla ASIC+LUT flow. The useful regime arises only when a carefully chosen subset of standard cells is selected so that the mapped structure becomes more LUT-friendly. FuseMap therefore frames cell selection as a bandit problem over a standard-cell library $k$ 25, supports $k$ 26, delay, and area-delay product minimization, defines $k$ 27, and uses $k$ 28-greedy and UCB strategies to update cell-selection probabilities (Yu, 15 Jul 2025).

On a 24-design ASAP7 evaluation, the paper reports $k$ 29 improvement in 20 out of 24 designs, average $k$ 30 improvement of about $k$ 31, average delay improvement around $k$ 32, and average ADP improvement around $k$ 33. It also reports convergence usually within 10–12 iterations and notes that aggressive shrinking of the library can increase the probability of failed mapping (Yu, 15 Jul 2025). The underlying message is that multi-input LUT realization quality depends strongly on the intermediate structure exposed to the mapper.

Across the surveyed literature, several recurring tradeoffs appear. First, direct lookup is rarely the whole story: the decisive issue is how the address space is engineered. LUT-NN requires end-to-end centroid learning rather than vanilla PQ; Hawk uses either one-time masks or noisy EC-derived reusable keys; the unified quantum architecture requires parameterized routing and CSWAP-based error containment; and FuseMap relies on design-specific cell subset selection rather than generic library use (Tang et al., 2023, Saleem et al., 2024, Zhu et al., 2024, Yu, 15 Jul 2025). Second, multi-input generality often creates exponential pressure. Table size grows exponentially with input precision or arity in Tabula and TableNet, the unary-iterate quantum lookup is exponential in address width $k$ 34, and Hawk treats $k$ 35 through two univariate tables precisely to avoid a huge multivariate LUT (Lam et al., 2022, Wu, 2019, Häner et al., 2022, Saleem et al., 2024). Third, performance gains are usually contingent on hardware-conscious layout or execution: SIMD shuffle instructions in LUT-NN, cache-aware streamed lookup in Vec-LUT, lattice-surgery routing in surface-code lookup, and nearest-neighbor planar layout in the unified quantum architecture (Tang et al., 2023, Li et al., 6 Dec 2025, Häner et al., 2022, Zhu et al., 2024).

A plausible implication is that the enduring significance of multi-input lookup-table protocols lies less in any single implementation and more in a general design principle: when repeated computation can be reorganized into structured address formation plus retrieval, the dominant costs shift from arithmetic to representation, routing, security, or memory locality. The modern literature shows this principle operating in approximation-aware DNN inference, private nonlinear computation, fault-tolerant quantum data access, and FPGA logic packing, with each domain defining its own notion of what the “multiple inputs” are and what constraints make lookup preferable to direct computation.