LUT-Dense: FPGA-Optimized Dense Neural Layer

• LUT-Dense is a dense neural layer that replaces conventional multiplications with learned 1-input LUTs, achieving universal approximation through dense connectivity and parallel LUT lookup followed by summation.
• The training process uses small per-edge MLPs with HGQ quantizers to approximate each scalar connection, enabling gradient-based optimization, fine-grained sparsity, and automatic pruning.
• After training, the learned mappings are compiled into FPGA logical LUTs with resource-aware optimization, delivering significant speedups and efficient deployment in hybrid architectures.

LUT-Dense is a dense (fully connected) neural network layer in HGQ-LUT in which neuron-to-neuron connections are implemented as learned 1-input logical lookup tables (L-LUTs) rather than multipliers and adders. During training, each scalar connection is represented by a small MLP and optimized jointly with HGQ quantizers; after training, the learned mappings are compiled into FPGA logic LUTs. In this formulation, the layer realizes dense connectivity as parallel LUT lookups followed by summation, eliminates multiplications and MACs inside the LUT-Dense block, and serves as a logic-oriented substrate for ultra-low-latency FPGA inference and hybrid FPGA neural architectures (Sun et al., 24 Apr 2026).

1. Formal definition and relation to dense layers

For a layer $l$ with $N$ inputs, LUT-Dense is defined as

$$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$

where $a^{(l-1)}_j$ is the activation of input neuron $j$ in the previous layer, $a^{(l)}_i$ is the activation of output neuron $i$, and $\text{L-LUT}_{i,j}$ is a learned 1-input LUT mapping the scalar $a^{(l-1)}_j$ to a scalar contribution for output $i$. Each pair $N$0 therefore carries its own scalar non-linear function, and the output neuron aggregates these functions by summation (Sun et al., 24 Apr 2026).

The construction is explicitly related to a standard dense layer. A conventional dense layer is

$N$1

and the reparameterized form used by the authors is

$N$2

If each 1-input LUT is defined as

$N$3

then substitution into the LUT-Dense definition recovers the reparameterized dense layer exactly. On that basis, the paper states that LUT-Dense is functionally at least as expressive as a standard dense layer and that universal approximation is preserved. Conceptually, it is a relaxation of a dense layer in which each scalar connection is replaced by a more general scalar non-linear function.

A recurrent misconception is to equate LUT-Dense with a high-fan-in LUT neuron. The defining unit is instead the 1-input L-LUT on each edge, not a multi-input Boolean blob. Expressivity is recovered through dense connectivity, summation across inputs, and stacking of LUT-Dense layers. This places the non-linearity on the edge functions while preserving the dense graph structure of the layer.

2. Training-time parameterization and quantization semantics

At training time, each $N$4 is not stored as a discrete truth table. It is represented by a small MLP with one input and one output: $N$5 where $N$6 is the batch index, $N$7 and $N$8 are the MLP parameters, and $N$9 is typically $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$0. The typical configuration uses only one hidden layer, $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$1. This makes the training object a dense tensor program rather than a direct combinational-logic synthesis problem (Sun et al., 24 Apr 2026).

The forward pass of the layer is organized as regular tensor operations: broadcast and quantize the inputs, pass them through the internal MLPs that realize all $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$2, optionally batch-normalize, quantize outputs, and sum over the input dimension. In the paper’s pseudocode, the input $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$3 has shape $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$4, the output $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$5 has shape $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$6, and the computation uses broadcast, einsum, optional batch normalization, output quantization, and a final reduction over the input-channel axis.

Quantization is integral to the layer semantics. Each L-LUT has separate input and output quantizers. The input quantizer $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$7 is applied to the broadcasted inputs and uses WRAP mode to avoid comparators at inference; the output quantizer $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$8 is applied to L-LUT outputs and uses SAT mode to clamp outputs to a smaller bit-width. Both are HGQ quantizers with element-wise trainable bit-widths. The framework permits 0-bit quantization. If, for a connection $$a^{(l)}_i = \sum_{j=1}^{N} \text{L-LUT}_{i,j}\!\left(a^{(l-1)}_j\right),$$9, either the input quantizer or the output quantizer is set to 0 bits, that L-LUT is pruned and disappears in hardware.

This quantization scheme gives LUT-Dense a dual interpretation. On the algorithmic side, the learned MLP realizes a floating-point surrogate of the scalar function. On the hardware side, the learned input and output precisions define the discrete address space and value space of the future truth table. The paper’s wrap-quantization approximation,

$a^{(l-1)}_j$0

captures the logic of the inference-time addressing path, while the actual training procedure uses differentiable surrogates and STE.

Backpropagation remains standard. The internal MLP parameters are ordinary floating-point tensors, gradients flow through them via autodiff, and the final summation is linear. No special gradient logic is required beyond HGQ’s quantizer STE. This is an important practical distinction between LUT-Dense and training schemes that directly manipulate discrete truth tables.

3. GPU-efficient realization and automatic sparsification

The defining practical claim of LUT-Dense is that LUT-aware training can be reduced to regular accelerator-efficient tensor operations. Three design choices are central. First, the layer uses only 1-input L-LUTs; compared to high fan-in LUTs, these can be modeled by very small MLPs with one hidden layer and small width. Second, connectivity is dense and static during training: all possible input-output mappings $a^{(l-1)}_j$1 are instantiated, then pruned by quantization, rather than dynamically rewired with irregular scatter/gather. Third, the implementation uses einsum-based operations that can be fused into optimized kernels by JAX/XLA or similar compilers. The resulting training complexity is close to a regular MLP of size $a^{(l-1)}_j$2 with small hidden dimension (Sun et al., 24 Apr 2026).

This architectural choice directly addresses the two bottlenecks identified in prior LUT-aware training approaches such as NeuraLUT-Assemble. Earlier LAT methods use multi-input L-LUTs that must be approximated during training by relatively wide and deep MLPs, and often treat the mapping of LUTs itself as trainable, requiring dynamic scatter/gather. LUT-Dense instead recovers expressivity by using many 1-input LUTs, dense connectivity, and summation as reduction, while relying on heterogeneous quantization and 0-bit pruning to remove unneeded connections. The measured result reported in the paper is that HGQ-LUT with LUT-Dense is about 197× faster than NLA on the shared benchmark and comparable in speed to plain HGQ.

Element-wise heterogeneous quantization induces fine-grained sparsity. Each scalar in the quantized tensor can have its own bit-width, these bit-widths are optimized jointly with the weights via gradient descent plus a resource penalty, and 0-bit values remove corresponding L-LUTs. If the input quantizer for $a^{(l-1)}_j$3 is 0-bit, the L-LUT never receives nonzero input; if the output quantizer is 0-bit, its output is always zero. In both cases, the connection is redundant and is removed in the final hardware mapping. This yields sparsity at the level of individual scalar edge functions rather than only at the level of neurons or blocks.

A plausible implication is that LUT-Dense makes sparsity discovery hardware-aligned by construction. The same mechanism that suppresses unnecessary scalar mappings in training also reduces the number of logic LUTs in synthesis, because pruned edge functions simply cease to exist as truth tables.

4. Compilation into logic LUTs and resource-aware optimization

After training, each LUT-Dense layer is converted into a network of logic LUTs. For each L-LUT $a^{(l-1)}_j$4, the compiler determines the trained input bit-width $a^{(l-1)}_j$5 and output bit-width $a^{(l-1)}_j$6, enumerates all $a^{(l-1)}_j$7 possible input codes, evaluates the learned MLP at each decoded fixed-point input, applies the output quantizer in SAT mode, and stores the resulting $a^{(l-1)}_j$8-bit outputs in a truth table of shape $a^{(l-1)}_j$9. The paper notes that all L-LUTs in the same layer with the same input width are processed in parallel via a single einsum-based evaluation, and reports that conversion for a typical 32×32 LUT-layer on a modern CPU is approximately $j$0 ms (Sun et al., 24 Apr 2026).

The mapping to FPGA logic follows the physical LUT fabric. The quantized input is an $j$1-bit word, the quantized output is an $j$2-bit word, and the truth table has $j$3 entries of width $j$4. Physical LUT primitives such as 6-input LUTs in Xilinx Ultrascale store fragments of this table, while built-in cascade multiplexers such as F7/F8/F9 support wider logical inputs. The dense connectivity of the neural layer is therefore realized as parallel LUT lookups followed by an adder tree or simple summation per output neuron. The arithmetic path differs fundamentally from a conventional dense layer implementation, which would use DSPs or LUT-based multipliers and runtime MACs.

Resource modeling is built into the training objective. HGQ uses Effective Bit Operations (EBOPs) as a differentiable proxy for hardware cost, and for LUT-Dense extends this with the analytical model

$j$5

where $j$6 is the FPGA LUT primitive size and $j$7 is a smaller logical LUT size used in the packing approximation. At the layer level,

$j$8

Empirically, the paper reports a nearly linear relationship between $j$9 and $a^{(l)}_i$0,

$a^{(l)}_i$1

This surrogate appears in the total training loss,

$a^{(l)}_i$2

where $a^{(l)}_i$3 is swept during a single training run to explore accuracy-resource trade-offs. Increasing $a^{(l)}_i$4 pushes the model toward lower bit-widths, more 0-bit quantizers, and more pruning, thereby producing an automated Pareto frontier of accuracy versus LUT usage without manual bit-width tuning.

The compilation flow is integrated into open-source tooling. On the algorithm side, LUT-Dense is a first-class layer type in HGQ2/HGQ. On the hardware side, models are lowered into da4ml’s DAIS IR with an instruction type L-LUT, then converted to RTL. The DAIS interpreter supports bit-exact simulation of L-LUT instructions on CPU up to 64-bit internal precision, and the workflow includes model definition and training, model selection from the Pareto frontier, export to DAIS IR, bit-exact simulation, and Verilog/VHDL generation.

5. Architectural role, hybrid deployments, and empirical behavior

Within HGQ-LUT, LUT-Dense is one of the two new LUT-based layers, the other being LUT-Conv. LUT-Conv is obtained by applying im2col to the input and feeding the unfolded patches into a LUT-Dense layer, so LUT-Dense serves as the core abstraction for both fully connected and convolution-like logic blocks. This permits pure LUT networks and hybrid networks that mix LUT-Dense with conventional matmul layers in the same HGQ/da4ml workflow (Sun et al., 24 Apr 2026).

The paper reports several concrete usage patterns. For the 16-feature HLF jet substructure classification task, it uses a 2-layer architecture with LUT-Dense layers of sizes 20 and 5. For particle-level jet tagging, LUT-Dense replaces all EinsumDense layers in a JEDI-Linear-like architecture, yielding latency and LUT usage significantly better than matmul-based HGQ and other neural baselines, while accuracy remains within approximately $a^{(l)}_i$5 to $a^{(l)}_i$6 of the best larger matmul-based models. For TGC muon tracking, where raw inputs are high-dimensional but low-information, the recommended pattern is a hybrid architecture: conventional dense layers for early feature extraction, then LUT-Dense as the output head. In that setting, the reported result is the same regression accuracy as a full HGQ dense head with approximately one-third lower latency and approximately one-quarter lower LUT usage on the FPGA.

For cluster counting and PID on CEPC gas detector waveforms, the architecture uses a conventional 1D convolution to reduce bit-width and local complexity, then several LUT-Conv layers built on LUT-Dense together with a time-dependent LUT. Under a budget below $a^{(l)}_i$7k LUTs, the reported implementation uses 6813 LUTs, 1 DSP, 0 BRAMs, and 903 FFs, with $a^{(l)}_i$8 MHz, latency 154 cycles, and initiation interval 151 cycles. The resulting separation power is reported as better than traditional offline reconstruction, though below large LSTMs which are not hardware-practical.

On HLF JSC, LUT-Dense-based architectures are reported to yield the best Pareto frontier in accuracy versus LUT usage, dominating prior neural, LUT-based, decision-tree, and symbolic methods. Especially in low-LUT regimes below a few kLUTs, they achieve higher accuracy at lower LUT count and similar latency to state-of-the-art LAT. The training-speed result, again, is that HGQ-LUT using LUT-Dense trains approximately 197× faster than NLA and at similar speed to plain HGQ.

The limitations stated in the paper are specific. Pure LUT-Dense on very high-dimensional, very sparse, or binary inputs can hurt accuracy; hybrid architectures with a dense front and a LUT head are recommended. The hidden dimension of the per-edge L-LUT MLPs is typically small, with one hidden layer and narrow width, so performance may saturate when extremely complex per-input functions are required.

6. Position within the broader LUT-based literature

LUT-Dense belongs to a broader class of LUT-based neural and matrix-computation designs, but its formulation is distinctive. In HGQ-LUT, a dense layer is decomposed into a sum of learned 1-input edge functions compiled into logic LUTs. KANELÉ adopts a closely related edge-centric viewpoint for Kolmogorov-Arnold Networks: each edge carries a learned 1D function on a fixed domain, each surviving edge is mapped to an L-LUT, and nodes only sum incoming edge outputs. The KANELÉ paper is explicit that such edge functions are “not merely approximated by a L-LUT: it is a lookup table,” and that the resulting architecture is a dense graph where every edge is implemented as a discrete LUT mapping (Hoang et al., 14 Dec 2025).

Other LUT-DNN lines attack different bottlenecks. SparseLUT retains small LUT fan-in and improves hardware efficiency by aggregating multiple PolyLUT sub-neurons with an adder and by learning sparse connectivity under a fixed fan-in constraint, reporting LUT reductions of $a^{(l)}_i$9 to $i$0 and latency reductions of $i$1 to $i$2 while maintaining comparable accuracy (Lou et al., 14 Jan 2026). MuLUT constructs a “DNN of LUTs” for image restoration by combining multiple LUTs in parallel and cascade, using complementary indexing patterns, re-indexing, and channel indexing so that total size is linear in indexing capacity rather than exponential in a single LUT’s index dimension (Li et al., 2023). These approaches share the objective of escaping the combinatorial blow-up of monolithic LUTs, but they do so through multi-LUT composition, sparse connectivity, or task-specific spatial indexing rather than through per-edge 1-input scalar functions.

A different branch of the literature uses LUTs to accelerate dense GEMM and LLM inference rather than to define neural layers directly. FIGLUT replaces FP-INT GEMM arithmetic with pattern-to-sum LUT retrieval in a custom accelerator (Park et al., 10 Mar 2025). PALUTE stores LUTs inside Monolithic 3D DRAM and performs in-DRAM LUT queries for GEMM segments and unary nonlinear operators (Tian et al., 8 Jun 2026). Platinum uses offline-generated construction paths and adaptive path switching for ultra-low-bit LUT-based matrix multiplication (Shan et al., 26 Nov 2025), and ELUTQ introduces Hierarchical Linear Quantization so that non-uniform low-bit weights remain compatible with bit-serial LUT-GEMM on CPUs (Nie et al., 22 Oct 2025). These systems also realize “dense” computation through lookup, but the lookup granularity is typically a segmental dot product or operator approximation, not the learned scalar edge function of LUT-Dense.

This comparison clarifies the specific niche of LUT-Dense. It is neither a monolithic LUT neuron nor a GEMM accelerator abstraction. It is a neural-layer construction in which dense connectivity is preserved, each scalar connection becomes a learned 1-input logical LUT, training remains expressible as regular tensor programs, and compilation targets FPGA logic LUTs directly. This suggests that LUT-Dense is best understood as an FPGA-oriented, edge-function generalization of the dense layer rather than as a generic synonym for LUT-based dense computation.