Heron Quantum Processor

• Heron Quantum Processor is a family of IBM superconducting devices using transmon qubits arranged in heavy-hex lattice configurations with variable qubit counts.
• It is evaluated through rigorous benchmarking frameworks including Grover search, layer-fidelity measures, and protocol-based tests to assess operational performance.
• The processors leverage advanced noise calibration and mitigation strategies such as dynamical decoupling and error extrapolation to optimize quantum circuit fidelity.

Heron Quantum Processor denotes a family of IBM superconducting quantum processors that has been studied through hardware benchmarks, end-to-end quantum-information protocols, algorithmic demonstrations, digital simulation, and large-scale hybrid quantum-classical workflows. In the cited literature, Heron systems appear in several reported configurations, including 27-qubit, 127-qubit, 133-qubit, and 156-qubit devices, with transmon-based implementations, nearest-neighbor coupling, and backend-dependent two-qubit control based either on tunable couplers or cross-resonance operations. Across these studies, Heron serves less as a single immutable hardware specification than as a processor family whose revisions are evaluated by workload-level performance, crosstalk-aware fidelity metrics, and application-oriented benchmarks (McKay et al., 2023, Tenev et al., 25 Apr 2026, Shirakawa et al., 31 Oct 2025).

1. Family designation and reported variants

The literature does not present a single, fixed Heron specification. Instead, multiple papers describe distinct Heron backends, revisions, and sub-registers used for different experimental purposes. Reported instances include Heron r1 “Torino,” Heron r2 “Marrakesh,” and Heron r3 “Pittsburgh” in a Grover-search study; the 133-qubit processor ibm_montecarlo in large-scale layer-fidelity benchmarking; Heron-r2 “Kingston” in protocol-based benchmarking; ibm_marrakesh and ibm_kobe in hybrid chemistry calculations; and a 156-qubit Heron r3 device accessed via ibm_pittsburgh in quantum hyperdimensional computing (Tenev et al., 25 Apr 2026, McKay et al., 2023, Mayo et al., 4 Mar 2026, Shirakawa et al., 31 Oct 2025, Cumbo et al., 16 Nov 2025).

Reported device	Reported specification	Reported use
Heron r1 “Torino”	27 superconducting qubits, heavy-hex lattice	Grover benchmarks
Heron r2 “Marrakesh”	27 qubits, same topology	Grover benchmarks
Heron r3 “Pittsburgh”	127 qubits, heavy-hex lattice	Grover benchmarks
ibm_montecarlo	133-qubit tunable-coupling Heron	Layer-fidelity benchmark
Heron-r2 “Kingston”	156 superconducting transmon qubits	Protocol-based benchmark
ibm_marrakesh / ibm_kobe	156 tunable transmon qubits, heavy-hex	Closed-loop chemistry workflow

Additional studies focus on structured sub-registers rather than whole-chip characterization. A Heron 2 benchmarking study selected a 6-qubit sub-register forming a closed ring, chosen to match a 6-site Hubbard-like lattice for Wigner-dimer simulation, while Grover experiments used an $n$-qubit “star” sub-graph with one central qubit connected to $n-1$ leaves in order to minimize SWAP overhead in multi-control-$Z$ decompositions (Kiiamov et al., 3 Jan 2026, Tenev et al., 25 Apr 2026).

This suggests that “Heron” functions in practice as a family label spanning several calibrated processors and revisions rather than a single processor with one canonical qubit count or one canonical coupling graph.

2. Architecture, connectivity, and native control

Several Heron studies describe superconducting transmon architectures with sparse planar connectivity. One account of Heron 2 specifies fixed-frequency transmons with individual flux lines, arranged in a planar 2D array, with tunable couplers between nearest neighbors. In that study, each nearest-neighbor pair is bridged by a third, flux-tunable transmon coupler, and the effective interaction is written in the rotating frame as

$$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$

where $g(\Phi_c)$ is the transverse exchange rate and $\chi(\Phi_c)$ is the residual static $ZZ$ interaction (Kiiamov et al., 3 Jan 2026).

The 133-qubit Heron benchmark identifies a heavy-hexagon lattice with fixed-frequency transmon qubits and tunable couplers, emphasizing that the qubit-qubit $ZZ$ interaction can be effectively “turned off” when no two-qubit gate is desired. That work reports microwave-activated CZ as the native two-qubit gate, with CZ durations of 84 ns or 104 ns, single-qubit Clifford gates of 35 ns, and arbitrary $z$ rotations implemented by frame updates (McKay et al., 2023). By contrast, the protocol-based comparison of Heron-r2 “Kingston” describes a sparse 2D lattice built from repeated 12-qubit rectangles, with calibrated microwave pulses implementing the IBM “U1, U2, U3” basis and cross-resonance CNOT (CX) between nearest-neighbor pairs (Mayo et al., 4 Mar 2026). A QHDC implementation on a 156-qubit Heron r3 device also reports heavy-hex connectivity and native CNOTs on specified edges, with single-qubit gate durations of 30–50 ns, two-qubit CNOT durations of 200–400 ns, and readout pulses of approximately 1–2 $\mu$s (Cumbo et al., 16 Nov 2025).

These descriptions are not identical, but they are consistent in a broader architectural sense: Heron processors are reported as sparse superconducting lattices whose practical performance depends strongly on mapping quantum circuits onto favorable subgraphs. The workload-specific choices of star subgraphs, hexagonal rings, and rectangular sub-chips indicate that routing overhead is a first-order concern rather than an implementation detail (Tenev et al., 25 Apr 2026, Kiiamov et al., 3 Jan 2026, Mayo et al., 4 Mar 2026).

3. Calibration, coherence, and noise characterization

The most explicit revision-by-revision calibration data appear in the Grover study of three Heron generations. For the 3-qubit star used there, Heron r1 “Torino” is reported with mean $n-1$0s, minimum $n-1$1s, mean $n-1$2s, minimum $n-1$3s, mean readout error $n-1$4, and mean two-qubit error $n-1$5. Heron r2 “Marrakesh” is reported with mean $n-1$6s, minimum $n-1$7s, mean $n-1$8s, minimum $n-1$9s, mean readout error $Z$0, and mean two-qubit error $Z$1. Heron r3 “Pittsburgh” is reported with mean $Z$2s, minimum $Z$3s, mean $Z$4s, minimum $Z$5s, mean readout error $Z$6, and mean two-qubit error $Z$7 (Tenev et al., 25 Apr 2026).

Other studies give device-level calibration in different forms. Heron-r2 “Kingston,” using a typical November 2025 calibration, is described with $Z$8 values of 80–150 $Z$9s, median approximately 120 $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$0s; $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$1 values of 60–120 $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$2s, median approximately 90 $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$3s; single-qubit gate error of 0.1–0.3%; CNOT error of 0.8–2.0%; and readout error of 1–3% (Mayo et al., 4 Mar 2026). The 156-qubit Heron r3 QHDC study reports nightly-calibration values of $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$4–120 $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$5s, $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$6–90 $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$7s, single-qubit gate error on the order of $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$8 to $$H_c(\Phi_c) \simeq g(\Phi_c)\,(\sigma_i^+ \sigma_j^- + \sigma_i^- \sigma_j^+) + \chi(\Phi_c)\,\sigma_i^z \sigma_j^z,$$9, two-qubit CNOT error $g(\Phi_c)$0, and readout assignment fidelities typically 95–98% (Cumbo et al., 16 Nov 2025).

Noise characterization in Heron-based hybrid workflows is also application-specific. In the chemistry workflow coupled to Fugaku, single-qubit error rates $g(\Phi_c)$1 were taken from randomized benchmarking, two-qubit error rates $g(\Phi_c)$2 from layer-fidelity tomography on each physical coupling, and SPAM error $g(\Phi_c)$3 from all-zero and all-one calibration shots. These fed an estimated circuit fidelity

$g(\Phi_c)$4

which was used in dynamic qubit mapping to select a high-fidelity 77-qubit subset (Shirakawa et al., 31 Oct 2025).

Taken together, these reports show that Heron performance is best understood through calibrated subgraph selection, workload-aware compilation, and live noise-model construction rather than through a single static specification sheet.

4. Benchmarking frameworks and system-level performance

A central Heron benchmark is the crosstalk-aware layer-fidelity protocol introduced for large processors. In simultaneous direct randomized benchmarking over disjoint layers, the process fidelity for each pair or idle-qubit map is extracted from an exponential parameter $g(\Phi_c)$5, and the sublayer and full-layer fidelities are defined as

$g(\Phi_c)$6

The size-independent error per layered gate is then

$g(\Phi_c)$7

and the probabilistic error-cancellation overhead scales as $g(\Phi_c)$8 under a depolarizing approximation (McKay et al., 2023).

Applied to the 133-qubit Heron processor ibm_montecarlo, this benchmark yielded $g(\Phi_c)$9 with $\chi(\Phi_c)$0 and $\chi(\Phi_c)$1 with $\chi(\Phi_c)$2. The same study interprets these values as indicating relatively high parallel performance up to about 80 qubits, with deeper circuits beyond about 100 qubits becoming impractical without additional mitigation (McKay et al., 2023).

A distinct benchmarking strategy evaluates end-to-end quantum-information protocols against classical fidelity thresholds. For Heron-r2 “Kingston,” six protocols were studied: Transmit, Do-nothing, Bell-state transfer, Teleportation, Super-dense coding, and Entanglement swapping. The thresholds were $\chi(\Phi_c)$3 for single-qubit transfer, teleportation, super-dense coding, and entanglement swapping, and $\chi(\Phi_c)$4 for Bell-state transfer. On single-rectangle sub-chips, Heron “Kingston” reported $\chi(\Phi_c)$5 values of $\chi(\Phi_c)$6 for Transmit, $\chi(\Phi_c)$7 for Do-nothing, $\chi(\Phi_c)$8 for Teleportation, $\chi(\Phi_c)$9 for Bell-state transfer, $ZZ$0 for Super-dense coding, and $ZZ$1 for Entanglement swapping. Its chip-level Scores were 0.524, 0.431, 0.416, 0.422, 0.297, and 0.309 respectively, all exceeding the corresponding Eagle scores in that comparison (Mayo et al., 4 Mar 2026).

These two frameworks measure different operational regimes. Layer fidelity isolates large-scale parallel gate performance with explicit sensitivity to crosstalk, whereas protocol-based benchmarking tests whether end-to-end information-processing tasks exceed classical limits on specific sub-chips. A common misconception is that a large qubit count alone determines useful performance; the Heron results show instead that usable depth, crosstalk behavior, and pass yield over selected subgraphs are the decisive quantities.

5. Algorithmic demonstrations and scientific simulation

Heron processors have been used as direct algorithmic benchmarks. In the three-generation Grover study, the implemented single-target search used

$ZZ$2

with Grover iterate $ZZ$3, and theoretical success probability

$ZZ$4

Using 10 000-shot experiments and target bitstrings “010”, “0101”, and “01011”, the no-dynamical-decoupling peak single-iterate results were, for $ZZ$5, $ZZ$6 on r1, $ZZ$7 on r2, and $ZZ$8 on r3; for $ZZ$9, $ZZ$0, $ZZ$1, and $ZZ$2; and for $ZZ$3, $ZZ$4, $ZZ$5, and $ZZ$6. For $ZZ$7, r1 and r2 peaked at $ZZ$8 rather than the theoretical $ZZ$9, while r3 peaked at $z$0 with $z$1 (Tenev et al., 25 Apr 2026).

The same work examined topological dynamical decoupling. On r1, the best $z$2 yielded approximately 30% uplift over the free case; on r2, XY4 $z$3 gave the largest boost; and on r3, CPMG hurt performance, XY4 raised $z$4 over free, and $z$5 slightly outperformed XY4 with peak $z$6 versus 0.35 free. In the six-qubit r3 experiment with target “010110” and random-guess threshold $z$7, the bare-hardware run at $z$8 gave $z$9, whereas XY4 and $\mu$0 raised this to approximately 0.055 and 0.060 respectively. The DD-protected histograms placed the true target well above all other bitstrings (Tenev et al., 25 Apr 2026).

Heron 2 has also been used for digital quantum simulation of Wigner localisation in a quasi-1D electron system. In that study, a 6-qubit ring sub-register implemented a mapped Coulomb-Hubbard Hamiltonian,

$\mu$1

with exact energies compared against experimental values across $\mu$2. The reported relative error fell monotonically from 10.65% at $\mu$3 to 6.19% at $\mu$4, and the combination of zero-noise extrapolation plus dynamical decoupling was described as critical, since without them the relative error in the computed energies would have exceeded 15% in the low-$\mu$5 regime (Kiiamov et al., 3 Jan 2026).

These demonstrations show Heron in two complementary roles: as a benchmark target for algorithmic depth and oracle-heavy circuits, and as a calibrated simulator for small many-body Hamiltonians whose error profile depends strongly on entanglement structure and mitigation strategy.

6. Hybrid supercomputing, neuromorphic experiments, and practical limits

Heron has also been embedded in full-scale closed-loop workflows with classical supercomputing. In the chemistry study with Fugaku, two Heron devices, ibm_marrakesh and ibm_kobe, each with 156 tunable transmon qubits in IBM heavy-hex connectivity, were used with a 77-qubit selected subset: 72 primary qubits encoding 36 spatial orbitals and 5 ancilla qubits mediating density-density interactions. The workflow used sample-based quantum diagonalization, Local Unitary Cluster Jastrow circuits, dynamic qubit mapping via a modified VF2++ heuristic, and a “fresh” noise model based on layer-fidelity tomography, SPAM calibration, and randomized benchmarking. LUCJ circuits on the full 77-qubit layout contained up to approximately 10 570 two-qubit gates; each circuit used 500 000–750 000 shots at a typical 10 $\mu$6s shot period; and the classical side scaled to 152 064 Fugaku nodes with projected subspace dimensions up to $\mu$7 determinants. The reported best raw and variance-extrapolated energies for [2Fe-2S] and [4Fe-4S] were benchmarked against DMRG references, including an improvement of 278 m$\mu$8 over prior quantum state of the art on 4Fe-4S.

A very different application area is quantum hyperdimensional computing. The Heron r3 QHDC study mapped hypervectors to quantum states via phase encoding, implemented binding through phase oracles, permutation through QFT, and similarity by the Hadamard Test. Full bundling via LCU plus oblivious amplitude amplification was found to be the principal bottleneck: for flat-LCU bundling of nine four-qubit states, the transpiled depth was reported as $\mu$9 with CNOT count $n-1$00, which was deemed infeasible on hardware. A hybrid workaround performed bundling classically and re-encoded the result into a single DiagonalGate. Under this strategy, Heron hardware execution achieved $n-1$01 for $n-1$02 using 7 system qubits plus ancilla over approximately 142 min total runtime, and $n-1$03 for a hardware-aware $n-1$04 version over approximately 52 min; the same study attributed the dominant error budget to decoherence and CX infidelity, with measurement-error mitigation recovering approximately 1–2% in raw fidelity and dynamical decoupling adding approximately 5 $n-1$05s of $n-1$06 extension on idles (Cumbo et al., 16 Nov 2025).

These results delimit the practical meaning of Heron’s current capabilities. High qubit count does not by itself guarantee support for deep coherent primitives, full-chip uniformity, or application-level scalability. The benchmark record instead indicates three recurring conditions for success: careful sub-chip or subgraph selection, compilation that respects the device geometry, and workload-specific mitigation such as dynamical decoupling, zero-noise extrapolation, gate twirling, or sample-based post-processing. A plausible implication is that Heron’s significance lies not only in nominal scale, but in its role as a testbed for quantitatively connecting hardware metrics, algorithm structure, and orchestration with large classical resources (Mayo et al., 4 Mar 2026, Shirakawa et al., 31 Oct 2025, Cumbo et al., 16 Nov 2025).