Complex-Instruction-Set Quantum Computer

• Complex-Instruction-Set Quantum Computer (CISQ) is a quantum architecture that exposes high-level, nonstandard instructions like QFT and Toffoli blocks to streamline multi-qubit operations.
• Methodologies involve using enriched native gate sets, macro-instructions, and co-designed controllers to reduce two-qubit gate counts and calibration overhead.
• CISQ enhances quantum program compilation by balancing expressivity with practical calibration limits, achieving significant improvements in gate fidelity and synthesis efficiency.

to=shell 񹚊pp code: {"command":["bash","-lc","python - <<'PY'\nimport urllib.request\nurl='http://export.arxiv.org/api/query?search_query=all:Complex-Instruction-Set+Quantum+Computer&start=0&max_results=3'\ntry:\n print(urllib.request.urlopen(url, timeout=20).read()[:500].decode())\nexcept Exception as e:\n print('ERR',e)\nPY"]} to=shell ҷкәын code: {"command":["bash","-lc","python - <<'PY'\nimport urllib.parse, urllib.request, xml.etree.ElementTree as ET\nqueries=[\n 'all:\"Complex-Instruction-Set Quantum\"',\n 'all:\"quantum instruction set\" AND all:performance',\n 'all:CISQ AND all:quantum',\n]\nns={'a':'http://www.w3.org/2005/Atom'}\nfor q in queries:\n url='http://export.arxiv.org/api/query?search_query=%s&start=0&max_results=5' % urllib.parse.quote(q)\n data=urllib.request.urlopen(url, timeout=20).read()\n root=ET.fromstring(data)\n print('\nQUERY',q)\n for e in root.findall('a:entry',ns):\n idurl=e.find('a:id',ns).text\n print(idurl.rsplit('/',1)[-1], e.find('a:title',ns).text.strip())\nPY"]} to=shell 大发时时彩怎么 code: {"command":["bash","-lc","python - <<'PY'\nimport urllib.parse, urllib.request\nq='all:\"Complex-Instruction-Set Quantum\"'\nurl='http://export.arxiv.org/api/query?search_query=%s&start=0&max_results=5' % urllib.parse.quote(q)\nprint(url)\ntext=urllib.request.urlopen(url, timeout=20).read().decode('utf-8','ignore')\nprint(text[:2000])\nPY"]} to=shell 总代理联系 code: {"command":["bash","-lc","echo hi"]} A Complex-Instruction-Set Quantum Computer (CISQ) is a quantum architecture in which the exposed instruction set is richer than a minimal universal basis, in close analogy to classical CISC design. Rather than forcing all programs through a small fixed repertoire of one- and two-qubit primitives, CISQ architectures expose higher-level, non-uniform, or continuously parameterized operations as instructions: examples in the literature include $QFT_n$, Toffoli-like blocks, logical error-correction cycles, application-specific multi-qubit macros, nonstandard entangling gates, and even the full two-qubit $SU(4)$ modulo local rotations (Britt et al., 2017, Yang et al., 10 Nov 2025). In current quantum-computing research, the term has therefore come to denote an ISA philosophy rather than a single machine organization: the same label is used for near-term hardware gate-set enrichment, variationally synthesized multi-qubit instructions, pulse-level controller ISAs, and fault-tolerant qLDPC modules that implement complex logical subroutines directly in code space (Huang et al., 2021, Lu et al., 2022, Yang et al., 15 Feb 2026).

1. Conceptual scope and architectural lineage

The basic contrast between quantum RISC and quantum CISQ is explicit in ISA-level work on QPUs. A RISC-style quantum ISA uses a small, fixed universal set, uniform instruction width, and strict segmentation between classical control and quantum registers, with an emphasis on pipelining. A CISC-style quantum ISA instead permits a larger, non-uniform instruction set, in which some instructions act on many qubits at once and may be implemented in hardware or microcode; representative examples given in the literature are $QFT_n$, $Toffoli_n$, and logical-qubit error-correction cycles (Britt et al., 2017). In that setting, the instruction-width budget is written as

$$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$

where $k$ is the number of addressed qubits and $p$ is the parameter payload. Fixed-width interfaces favor regular decoding and streaming, whereas variable-length encodings permit larger macro-instructions at the cost of more complex control logic (Britt et al., 2017).

This architectural idea appears in several distinct quantum contexts. In fault-tolerant gate synthesis, one CISC formulation enlarges the instruction set from Clifford operations plus a single $T$-state resource to Clifford operations plus direct magic states for $Z(\pi/2^k)$ gates for $2\le k\le k_{\max}$, thereby removing a large part of the compiling overhead for accurate $SU(4)$0-axis rotations (Landahl et al., 2013). In qLDPC fault-tolerant architectures, CISQ denotes an application-tailored ISA whose instructions are embedded as matrix automorphisms of a co-designed code block, so that arithmetic, table lookup, and magic-state-distillation subroutines become in-block logical operations with $SU(4)$1 logical-time latency (Yang et al., 15 Feb 2026). This suggests that “complex instruction” in quantum computing may refer to at least three distinct granularities: compiler-visible macro-gates, hardware-native nonstandard gates, and logical operations realized directly in encoded subspaces.

CISQ form	Representative instruction style	Representative papers
Macro-op ISA	$SU(4)$2, $SU(4)$3, logical EC cycles	(Britt et al., 2017)
Enriched native gate set	SQiSW, fSim families, continuous $SU(4)$4	(Huang et al., 2021, Yang et al., 10 Nov 2025)
Application-tailored FT logic	adders, lookups, MSD in qLDPC blocks	(Yang et al., 15 Feb 2026)

2. Formal criteria for instruction-set design

A central theme in CISQ work is that instruction-set design is not purely syntactic; it is evaluated through fidelity, synthesis cost, and calibration overhead. For two-qubit operations, one standard metric is the average-gate fidelity

$SU(4)$5

In randomized-benchmarking-style analyses, the survival signal is fitted as $SU(4)$6, and for two qubits the fidelity is extracted as $SU(4)$7 with $SU(4)$8 (Huang et al., 2021). These metrics matter especially in CISQ design because instruction enrichment is intended to reduce two-qubit count, and two-qubit errors typically dominate.

For expressivity analysis, two-qubit CISQ research relies heavily on the KAK decomposition. Any $SU(4)$9 may be written as

$QFT_n$0

with $QFT_n$1 in the Weyl chamber. This geometric representation makes it possible to compare different entangling instructions by the region of nonlocal content each can reach efficiently. Huang et al. define two synthesis-cost figures of merit: $QFT_n$2, the average number of native gates needed for a Haar-random $QFT_n$3, and $QFT_n$4, the average number for a random two-qubit Clifford (Huang et al., 2021). Related Cartan-coordinate work derives lower and upper bounds on conversion cost between native gates and target two-qubit operations and uses those bounds to accelerate exploration of the instruction-set design space by thousands of times relative to numerical search (Wu et al., 2024).

A second formal axis is the trade-off between expressivity and calibration burden. Murali et al. define the average two-qubit instruction cost

$QFT_n$5

where $QFT_n$6 is the minimum number of instructions from candidate set $QFT_n$7 needed to implement $QFT_n$8 to a fixed threshold. Their calibration model scales roughly linearly in the number of gate types, and for a Sycamore-like setting they instantiate this as $QFT_n$9 per day, so that $Toffoli_n$0 costs $Toffoli_n$1 h/day, $Toffoli_n$2 costs $Toffoli_n$3 h/day, and a full continuous family of roughly $Toffoli_n$4 types would cost $Toffoli_n$5 h/day (Murali et al., 2021). In CISQ, therefore, “more expressive” and “more practical” need not coincide.

3. Enriched two-qubit instruction sets in the NISQ regime

One concrete CISQ instantiation is the replacement of a mainstream entangling basis by a richer nearby instruction. On a fluxonium processor with native $Toffoli_n$6, Huang et al. calibrate and characterize its square root, $Toffoli_n$7, and show that the instruction set $Toffoli_n$8 is superior to $Toffoli_n$9 for generic two-qubit synthesis (Huang et al., 2021). They measure an $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$0 gate fidelity of up to $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$1 with an average of $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$2, and Haar-random two-qubit gates synthesized with $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$3 achieve an average fidelity of $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$4. Relative to $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$5 on the same processor, this corresponds to a $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$6 average error reduction for the interleaved gate and a $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$7 reduction for Haar-random two-qubit unitaries. The compilation reason is geometric: a generic $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$8 with Cartan coordinates $$\mathrm{inst\_width}=\mathrm{opcode\_width}+k\cdot \mathrm{addr\_bits}+p,$$9 can be synthesized with $k$0 SQ gates iff $k$1; otherwise exactly $k$2 SQ gates suffice, and under the Haar measure about $k$3 of $k$4 lies in the $k$5-SQ region. Accordingly, $k$6 versus $k$7.

The same design problem can be posed at the level of entire gate families rather than a single replacement. For Rigetti-style $k$8 and Google-style $k$9 families, numerical decomposition with NuOp shows that implementing $p$0–$p$1 two-qubit gate types is sufficient to achieve nearly the same expressivity as the full continuous family while reducing calibration overhead by two orders of magnitude (Murali et al., 2021). In those experiments, $p$2–$p$3 yields $p$4–$p$5 two-qubit gates per random $p$6, compared with $p$7 for the continuous family, while avoiding the prohibitive calibration schedule implied by hundreds of distinct gate types.

Analytical Cartan-coordinate design frameworks sharpen this point. They treat nonstandard two-qubit gates as points in the Weyl chamber, derive bounds on gate-conversion cost from their Cartan coordinates, and use constant-time compilation procedures rather than numerical optimization loops (Wu et al., 2024). A plausible implication is that CISQ gate-set design is becoming less heuristic: the question is no longer merely whether a nonstandard gate is calibratable, but whether its Cartan location gives a favorable balance among entangling power, exact padding of common target angles, and calibration complexity.

4. Continuous and variational CISQ

A stronger form of CISQ exposes multi-qubit or continuously parameterized instructions directly. QuVIS, the quantum variational instruction set, is defined as a catalogue of parametrized multi-qubit unitaries on up to $p$8 qubits, realized by optimizing the device’s native time-dependent Hamiltonian rather than decomposing through a fixed microinstruction set (Lu et al., 2022). The control model uses a transverse-Ising Hamiltonian,

$p$9

with target approximation obtained by minimizing $T$0. Fine-grained time optimization (FGTO) progressively refines the time grid to avoid local minima. In the reported Ising-chain examples, the total control-time slope for QFT scales as $T$1, $T$2, and $T$3, so QuVIS$T$4 runs in less than half the time of QuMIS. The corresponding error-growth exponents are $T$5, $T$6, and $T$7, reflecting algebraic suppression of accumulated error through depth reduction.

At the two-qubit extreme, continuous-$T$8 CISQ has recently been pushed from theory toward practical compilation and control. ReQISC adopts the instruction set “all of $T$9 up to local one-qubit rotations” and pairs it with a unified microarchitecture and compiler stack that implement arbitrary two-qubit gates in theoretically optimal duration for a given coupling Hamiltonian (Yang et al., 10 Nov 2025). Under an $Z(\pi/2^k)$0-coupling Hamiltonian $Z(\pi/2^k)$1, the standard three-CNOT route costs on average $Z(\pi/2^k)$2 to realize a Haar-random $Z(\pi/2^k)$3, whereas the direct ReQISC scheme achieves $Z(\pi/2^k)$4, a $Z(\pi/2^k)$5-fold reduction in average pulse duration. Across $Z(\pi/2^k)$6 programs from $Z(\pi/2^k)$7 categories, the reported end-to-end reductions are about $Z(\pi/2^k)$8–$Z(\pi/2^k)$9 in two-qubit gate count, $2\le k\le k_{\max}$0–$2\le k\le k_{\max}$1 in two-qubit depth, and $2\le k\le k_{\max}$2–$2\le k\le k_{\max}$3 in pulse duration.

A closely related “complex yet reduced” view is the AshN gate scheme for $2\le k\le k_{\max}$4-coupled qubits, which claims a continuous instruction set covering the full two-qubit $2\le k\le k_{\max}$5 while using one tunable analog gate family underneath (Chen et al., 2023). In that framework, the CNOT class is reached in time $2\le k\le k_{\max}$6, the Haar-average interaction time is $2\le k\le k_{\max}$7, and static $2\le k\le k_{\max}$8 error can be absorbed by parameter shifts in the control Hamiltonian. This suggests that, in quantum hardware, “complex” and “reduced” are not always opposites: a continuum of logical instructions may be backed by a compact physical control scheme.

5. Programming languages, controllers, and instruction delivery

CISQ is not limited to entangling-gate selection; it also appears in software-stack and controller design. The Quantum Abstract Machine and Quil unify quantum gates, measurement, classical logic, flow control, shared memory, and parametric gates inside a single assembly-like formalism (Smith et al., 2016). Instruction classes include static gates such as $2\le k\le k_{\max}$9, $SU(4)$00, and CNOT; parametric gates such as $SU(4)$01, $SU(4)$02, and $SU(4)$03; measurements; jumps; Boolean operations on classical memory; WAIT; and directives such as DEFGATE and DEFCIRCUIT. In that literature, the CISQ character lies in orthogonality and expressiveness: programs can contain hybrid classical/quantum control structure rather than being restricted to static gate lists.

At the pulse-delivery layer, a CISQ microarchitecture may mean an instruction-driven signal-synthesis engine. One scalable controller uses a fixed-width $SU(4)$04-bit microinstruction word with a $SU(4)$05-bit opcode, $SU(4)$06-bit channel mask, predicate bits for conditional execution, a $SU(4)$07-bit envelope identifier, a $SU(4)$08-bit duration field, and a $SU(4)$09-bit immediate field (Khammassi et al., 2022). Instructions include pulse-synthesis operations (STA, STF, STP, STAP), timing and synchronization (WAIT, SYNC), and readout (RDO). The controller runs on a common $SU(4)$10 ns tick, supports $SU(4)$11 RF/DC channels plus $SU(4)$12 ADC channels per FPGA unit, and has a fetch-to-DAC latency of $SU(4)$13 ns. In the reported comparison, an AWG-based sweep of $SU(4)$14k points costs more than $SU(4)$15 s because waveforms must be uploaded, whereas the CISQ controller can do the same sweep in $SU(4)$16s by updating parameters rather than pre-storing full waveforms.

Application-specific ISA extension is another recurring CISQ pattern. In a superconducting quantum accelerator co-designed for materials-science simulation, the instruction set was extended with a continuous single-qubit rotation $SU(4)$17 and a robust two-qubit $SU(4)$18 gate, together with dynamic gate-set and paging mechanisms that map requested rotations to calibrated waveforms at load time (Zou et al., 2020). The experimental evaluation ran $SU(4)$19 random instances of a disorder-induced metal-insulator-transition simulation; each instance used $SU(4)$20 two-qubit instructions and $SU(4)$21 single-qubit instructions, and the expected quantum dynamics were observed. More generally, this line of work treats CISQ as application–system–qubit co-design: the instruction set is shaped by algorithmic demand and by the finite waveform/codeword resources of the control electronics.

The same philosophy has also been extended beyond qubit-only hardware. Hybrid CV–DV processor proposals define fixed-width ISAs with separate qubit-only, CV-only, and hybrid instructions such as DISP, ROT, SQZ, CD, CR, JC, and CBS, thereby embedding bosonic and qubit controls within one abstract machine model (Liu et al., 2024). This broadens CISQ from a gate-model optimization problem to a heterogeneous quantum-architecture problem.

6. Fault-tolerant CISQ, co-processors, and recurrent points of debate

In fault-tolerant settings, CISQ often means reducing logical resource overhead by elevating frequently used non-Clifford or Clifford-heavy subroutines to instruction status. For accurate $SU(4)$22-axis rotations, one CISQ architecture augments Clifford operations with magic states for $SU(4)$23 gates for $SU(4)$24, using shortened quantum Reed–Muller codes of length $SU(4)$25 for distillation (Landahl et al., 2013). The reported distillation thresholds are $SU(4)$26 for $SU(4)$27, $SU(4)$28 for $SU(4)$29, $SU(4)$30 for $SU(4)$31, $SU(4)$32 for $SU(4)$33, and $SU(4)$34 for $SU(4)$35. Although the asymptotic scaling can favor a $SU(4)$36-only RISC strategy, the paper reports that for practical target errors and small $SU(4)$37, the CISC approach often uses fewer overall magic states, and for $SU(4)$38 and $SU(4)$39 it is superior throughout the physically relevant regime discussed there.

RASCqL pushes the same idea into qLDPC code design. It defines a reaction-time-limited CISQ ISA in which Clifford-heavy functional blocks are embedded as virtually implementable matrix automorphisms of tailored qLDPC codes, with logical latency dominated by one QEC cycle of duration $SU(4)$40 rather than long surgery or injection sequences (Yang et al., 15 Feb 2026). In this architecture, MAJ/UMA blocks, fan-outs, and weight-$SU(4)$41 Pauli measurements complete in $SU(4)$42 logical time, giving $SU(4)$43 space-time volumes. On reconfigurable neutral-atom arrays, the reported syndrome-extraction cycles are $SU(4)$44 ms for the $SU(4)$45 HGPS code and $SU(4)$46 ms for the $SU(4)$47 bicycle code, with a circuit-level threshold $SU(4)$48. For realistic physical error rates $SU(4)$49 to $SU(4)$50, the architecture reports $SU(4)$51 to $SU(4)$52 footprint reduction without additional hardware complexity.

A more modular interpretation appears in proposals for quantum co-processors that implement fixed Hamiltonian evolutions as supplementary instructions (Kay, 2017). There, instructions such as GHZ(n) or asymmetric quantum cloning are executed by dedicated devices whose couplings are engineered once and then invoked as one-line operations. For a $SU(4)$53-qubit GHZ co-processor, simulated GHZ overlap remains above $SU(4)$54 for about $SU(4)$55–$SU(4)$56 random engineering error in couplings and is still around $SU(4)$57 on average for about $SU(4)$58 error. This is a CISQ conception centered not on richer general-purpose programming, but on hardwired acceleration of recurrent subroutines.

Several recurrent debates follow from these lines of work. One common misconception is that CISQ simply means “more gate types.” The literature shows a broader picture: macro-op libraries, variational multi-qubit blocks, pulse-controller ISAs, fixed Hamiltonian co-processors, code-embedded logical operations, and continuous-$SU(4)$59 schemes all fall under the term in different subfields. A second misconception is that CISQ straightforwardly supersedes RISC. ISA analyses for QPUs argue instead that neither pure RISC nor pure CISC is ideal, and propose hybrid designs in which a universal low-level spine coexists with richer higher-level instructions (Britt et al., 2017). A third debate concerns calibration. Some results show that $SU(4)$60–$SU(4)$61 carefully chosen two-qubit instructions recover most of the benefit of a continuous family at far lower calibration cost (Murali et al., 2021); others argue that a continuous $SU(4)$62 ISA can nevertheless be made practical if the microarchitecture and compiler are co-designed to unify calibration and reuse instruction templates (Yang et al., 10 Nov 2025). Taken together, these results indicate that CISQ is best understood as a spectrum of architectural strategies for moving complexity away from long decompositions and into the instruction set, with the exact balance determined by hardware physics, compiler structure, and fault-tolerance constraints.