IQM Garnet Quantum Processor

• IQM Garnet Quantum Processor is a superconducting transmon-based QPU comprising 20 flux-tunable qubits arranged in a rotated square lattice for scalable control and entanglement.
• It employs a high-fidelity native gate set with 99.9% single-qubit and 99.5% two-qubit CZ operations, integrated with optimized pulse control and SWAP routing via the SABRE algorithm.
• The platform features robust calibration methods, comprehensive error characterization, and a modular design that enables scalability to 54 or 150 qubits for advanced quantum experiments.

The IQM Garnet Quantum Processor is a superconducting transmon-based quantum processing unit (QPU) developed by IQM Quantum Computers. With a 20-qubit "qubit crystal" architecture, the Garnet device integrates advanced hardware, firmware, and software approaches to enable high-fidelity gate operations, scalable qubit control, and multi-qubit entanglement suitable for near-term algorithmic benchmarks and quantum information experiments. The processor features a modular, tileable design focused on cryogenic integration, optimized coupler engineering, robust calibration infrastructure, and a complete control stack, with systematic characterization through multi-level performance benchmarks.

1. Hardware Architecture and Physical Implementation

The IQM Garnet QPU utilizes 20 flux-tunable transmon qubits arranged in a 45°-rotated square lattice, forming an effective 5×5 grid interleaved with flux-tunable transmon couplers. The lattice configuration yields 30 bidirectional edges, providing each qubit with approximately three nearest neighbors, facilitating gate routing while remaining conducive to surface-code operations (Abdurakhimov et al., 2024, Malarchick, 17 Jan 2026).

Physical qubit parameters are as follows:

• Transmon qubit: Josephson energy $E_J/h \approx 20$ GHz, charging energy $E_C/h \approx 200$ MHz, anharmonicity $\alpha \approx -200$ MHz.
• Idle and on-state ZZ coupling: Idle $<10$ kHz, activated $ZZ \approx 50$ MHz, adjusted via flux bias on tunable couplers.
• Coherence times: Median $T_1 = 40\,\mu$s ($10$–$90^\mathrm{th}$ percentile: $30$–$50\,\mu$s), median $E_C/h \approx 200$0s ($E_C/h \approx 200$1–$E_C/h \approx 200$2s) (Abdurakhimov et al., 2024). In independent work, $E_C/h \approx 200$3s, $E_C/h \approx 200$4s (Ramsey) (Malarchick, 17 Jan 2026).
• Qubit readout: Individual $E_C/h \approx 200$5 resonators ($E_C/h \approx 200$6: $E_C/h \approx 200$7–$E_C/h \approx 200$8 GHz), grouped into three frequency-multiplexed feedlines (7+7+6), each filtered via Purcell filters to minimize relaxation.
• Integration: 3D flip-chip packages route 76 control lines (drive, flux, readout) per QPU, with multi-layer magnetic shielding, terminated in a Bluefors XLD dilution refrigerator (base $E_C/h \approx 200$9 mK) (Abdurakhimov et al., 2024).

The logical-to-physical mapping and required SWAP operations respect this fixed connectivity through algorithms such as SABRE (Malarchick, 17 Jan 2026).

2. Native Gate Set and Pulse Control

The Garnet processor supports a high-fidelity native gate set, primarily comprising:

• PRX$\alpha \approx -200$0: Single-qubit $\alpha \approx -200$1 (or arbitrary) rotations about the $\alpha \approx -200$2 axis, implemented by Gaussian-enveloped DRAG pulses (pulse durations $\alpha \approx -200$3–$\alpha \approx -200$4 ns, $\alpha \approx -200$5 fidelity) (Malarchick, 17 Jan 2026, Abdurakhimov et al., 2024).
• CZ gates: Two-qubit entangling operations using flux-pulsed couplers or dynamically tuned cross-resonance interaction. Typical gate durations $\alpha \approx -200$6–$\alpha \approx -200$7 ns ($\alpha \approx -200$8% median fidelity), realized via flux bias activating the avoided crossing for a controlled-phase (Abdurakhimov et al., 2024).
• Virtual-Z (frame) gates: Implemented in software, enabling zero-duration $\alpha \approx -200$9 rotations for phase corrections and efficient compilation.

All higher-level unitaries (e.g., CNOT, arbitrary $<10$0) are decomposed into sequences of PRX and CZ gates. Pulse-level control is synthesized and modulated by a Python-based pulse compiler, parameterizing amplitude, frequency, phase, and duration (Malarchick, 17 Jan 2026).

Table 1: Native Gate Operations and Durations

Operation	Gate Duration	Fidelity
Single-qubit (PRX)	20–40 ns	99.9% (0.1% err)
Two-qubit (CZ)	20–40 ns	99.5% (0.5% err)

Pulse electronics comprise arbitrary waveform generators (AWG), digital-to-analog converters (DAC), sideband IQ mixing, and room-temperature signal conditioning, with real-time sequencing and triggering performed on field-programmable gate arrays (FPGA) (Abdurakhimov et al., 2024, Malarchick, 17 Jan 2026).

3. Calibration, Error Characterization, and Decoherence Modeling

Device characterization utilizes extensive calibration routines and benchmarking protocols:

• Process fidelity is defined as

$<10$1

where $<10$2 is derived by simulating the pulse sequence under a Lindblad master equation with time-dependent Hamiltonian terms and calibrated noise rates (Malarchick, 17 Jan 2026).

• Decoherence is described by Lindblad operators:

$<10$3

with $<10$4 (energy decay, $<10$5), $<10$6 (pure dephasing, $<10$7, $<10$8) (Malarchick, 17 Jan 2026).

Reported gate error rates are $<10$9 for single-qubit and $ZZ \approx 50$0 for native two-qubit gates, with crosstalk measured at median –70 dB (flux) and –48 dB (drive) (Abdurakhimov et al., 2024, Malarchick, 17 Jan 2026).

Multi-qubit entanglement is certified via preparation and measurement of Greenberger-Horne-Zeilinger (GHZ) states, with $ZZ \approx 50$1 qubits, and fidelity evaluated both with and without readout-error mitigation (REM). Raw GHZ fidelity drops below $ZZ \approx 50$2 for $ZZ \approx 50$3, but with REM, $ZZ \approx 50$4, satisfying the threshold for genuine 20-qubit entanglement (Abdurakhimov et al., 2024).

4. Compilation Stack and Circuit-Level Optimization

The compilation pipeline is closely integrated with hardware-specific constraints and pulse-level calibration. Mapping high-level circuits to hardware is performed by:

• Routing (SABRE algorithm): Inserts SWAPs to ensure circuit compliance with nearest-neighbor connectivity (Malarchick, 17 Jan 2026).
• Gate-level optimization passes: Four main transformations are benchmarked:
  • Gate cancellation: Removes adjacent inverse gates (e.g., $ZZ \approx 50$5), achieving $ZZ \approx 50$6 eliminated gates over $ZZ \approx 50$7 circuit runs, improving $ZZ \approx 50$8 of circuits.
  • Commutation analysis: Reorders commuting gates to expose further cancellation.
  • Rotation merging: Merges contiguous $ZZ \approx 50$9 rotations on the same qubit, eliminating $T_1 = 40\,\mu$0 gates ($T_1 = 40\,\mu$1 of circuits improved).
  • Identity elimination: Removes trivial single-qubit identities ($T_1 = 40\,\mu$2 gates, $T_1 = 40\,\mu$3 of circuits improved) (Malarchick, 17 Jan 2026).

Pulse-level simulations propagate these optimizations to the control sequence, allowing end-to-end fidelity analysis. Correlation analysis with circuit features shows that total pulse duration is the leading predictor of process fidelity (Pearson $T_1 = 40\,\mu$4, $T_1 = 40\,\mu$5); input gate count and circuit depth are also predictive but less so.

5. Benchmarking, Experimental Validation, and Quantum Volume

Comprehensive benchmarking is undertaken through both simulation and hardware execution:

• GHZ and QFT circuits: Experimental runs on the IQM Resonance Garnet device demonstrate job success rates of $T_1 = 40\,\mu$6 over $T_1 = 40\,\mu$7 runs. Gate cancellation provides minimal further optimization for inherently minimal circuits (GHZ), but achieves $T_1 = 40\,\mu$8 reduction (from $T_1 = 40\,\mu$9 to $10$0 gates) and $10$1 depth reduction (from $10$2 to $10$3) for QFT$10$4 circuits. Fidelity improvement is circuit dependent: QFT absolute fidelity remains low ($10$5) reflecting circuit complexity and cumulative decoherence, while GHZ$10$6 exhibits modest post-optimization gains ($10$7) (Malarchick, 17 Jan 2026).
• Quantum Volume (QV) and System CLOPS: System quantum volume is $10$8 (heavy-output probability $10$9). Virtual circuit layer operations per second (CLOPS) for $90^\mathrm{th}$0 is $90^\mathrm{th}$1 (Abdurakhimov et al., 2024).
• Entanglement Benchmarking: Certified 20-qubit entanglement is observed with GHZ state fidelity (REM applied) exceeding $90^\mathrm{th}$2 (Abdurakhimov et al., 2024).

Table 2: Summary of Core Performance Metrics

Metric	Value
Two-qubit gate fidelity	$90^\mathrm{th}$3 (median)
Single-qubit error	$90^\mathrm{th}$4 (median)
Crosstalk (flux/drive)	–70 dB/–48 dB
$90^\mathrm{th}$5 (median)	$90^\mathrm{th}$6s
$90^\mathrm{th}$7 (median)	$90^\mathrm{th}$8s
Quantum volume	$90^\mathrm{th}$9
GHZ(20) fidelity (REM)	$30$0

6. Application Studies and NISQ Algorithm Benchmarks

The hardware platform has been used for hardware-in-the-loop VQE and quantum simulation studies, including investigations of quantum phase transitions in the transverse-field Ising model (TFIM) (Sharma, 24 Jan 2026). In these applications:

• A depth-2, physics-inspired VQE ansatz was deployed on up to four physical qubits, using a resource-efficient batched protocol to ensure temporal calibration consistency.
• Hardware results reproduced qualitative ground-state energy trends and finite-size crossover, with shot-noise-limited error bars. However, hardware energy mean absolute errors ($30$1) systematically exceed those from ideal VQE, indicating significant impact from decoherence and control errors.
• Magnetic order parameters and long-range correlations suffer broadening and suppression, consistent with finite-temperature (noise) smearing.
• No additional error mitigation (readout or zero-noise extrapolation) is employed. These findings emphasize the importance of error mitigation for extraction of correlation-sensitive observables and highlight the current boundaries of NISQ-era hardware for quantitative many-body simulation (Sharma, 24 Jan 2026).

7. System Integration, Software Stack, and Scalability Roadmap

The full-stack design encompasses:

• Cryogenics and packaging: Bluefors XLD dilution refrigerator with cascaded RF attenuation, two-tier magnetic shielding, 3D QPU integration, and low-crosstalk control signal routing (Abdurakhimov et al., 2024).
• Control Electronics: IQM Quantum Control System (QCS) with modular AWGs, direct digital synthesizers, FPGAs for sequencing, and PXIe-based resource expansion.
• Software infrastructure: High-level job submission (OpenQASM, Qiskit, Cirq) via Cortex REST API; pulse-level experimentation and calibration using Python-based EXA; station control through systemd-integrated services. Remote access is facilitated by IP-KVM, UPS, firewalling, and automated monitoring.
• Scalability roadmap: Modular design enables scale-up to 54 and 150 qubits, employing hierarchical calibration (tile and system-level), crosstalk mitigation, enhanced thermal management, and FPGA-based resource aggregation. Calibration and drift tracking are targeted by machine learning methods and hierarchical routines (Abdurakhimov et al., 2024).

The consolidated technical benchmarks, from single- and two-qubit gate error characterization to system quantum volume and entanglement certification, render the IQM Garnet platform a representative state-of-the-art device for benchmarking the capabilities and practical limitations of superconducting quantum processors in the noisy intermediate-scale regime (Abdurakhimov et al., 2024, Malarchick, 17 Jan 2026, Sharma, 24 Jan 2026).