Quantinuum H2 Trapped-Ion Quantum Processor

Updated 28 November 2025

Quantinuum H2 is a trapped-ion quantum processor featuring full connectivity, high-fidelity gate operations, and long qubit coherence times.
It utilizes a linear chain of ^171Yb^+ ions with precisely controlled SU(2) rotations and native ZZPhase gates to perform advanced digital quantum simulations.
The system supports scalable quantum tasks, employing error mitigation techniques to achieve circuit depths and fidelities that exceed classical emulation.

The Quantinuum H2 series of trapped-ion quantum processors represents a leading platform for digital quantum simulation and certified randomness generation at the intermediate-scale (30–70 qubit) frontier. Utilizing linear chains of individually trapped ^171Yb⁺ ions, these devices feature all-to-all connectivity, high-fidelity native gate operations, and long single-qubit coherence times. The architecture and performance characteristics have enabled implementation of quantum tasks beyond practical classical emulation, including high-depth random circuit sampling, fermionic dynamics, and quantum phase estimation. The following sections comprehensively summarize the H2 system’s architecture, gate set, performance, error mitigation strategies, computational capabilities, and experimental benchmarks.

1. Device Architecture and Qubit Technology

The Quantinuum H2-1 and H2-2 processors are based on a linear Paul trap holding chains of ^171Yb⁺ ions, each encoding a single qubit via hyperfine “clock” transitions. Individual addressing is achieved with tightly focused laser beams, allowing arbitrary control of single-qubit SU(2) rotations as well as entangling operations between arbitrary pairs of ions.

The key architectural features are:

Qubit Register Size: Up to 56 trapped-ion qubits have been operated in a single string for quantum simulation tasks, with hardware extensibility to approximately 60–70 qubits (Alam et al., 30 Oct 2025).
Connectivity: The platform provides all-to-all qubit connectivity, realized by mediating multi-ion interactions through collective motional modes. Arbitrary pairs of qubits can be entangled directly, bypassing the need for explicit SWAP operations or planar routing constraints (Liu et al., 26 Mar 2025, Alam et al., 30 Oct 2025).
Trap Operations: Ions are cooled and can be re-cooled as necessary during mid-circuit operations. Shuttling is minimized in standard workflows, with logical SWAPs performed in software by qubit relabeling (Alam et al., 30 Oct 2025).
Qubit Encoding: Each qubit resides in a pair of hyperfine clock states, specifically designed to maximize coherence (T₁ > 30 s, T₂* ∼ 1 s, extendable to T₂ > 10 s via dynamical decoupling) (Alam et al., 30 Oct 2025).

2. Native Gate Set and Calibration

The H2 devices implement a native gate set that exploits the full flexibility of ion-trap technology:

Single-Qubit Operations: Arbitrary SU(2) gates, typically realized as composite rotations about X, Y, and Z axes. Errors per single-qubit gate are ≲3×10⁻⁵ (∼99.997% fidelity) (Alam et al., 30 Oct 2025), and up to 99.99% fidelity with SPAM errors ≲0.1% (Hémery et al., 2023).
Two-Qubit Gates: Native entangling gates are of the form ZZPhase or R_{zz}(θ) = exp[−(i/2)θ Z⊗Z], typically implemented with bichromatic Raman beams (Mølmer–Sørensen interaction). Calibrated two-qubit gate errors are ≲1×10⁻³ (∼99.90% fidelity) (Alam et al., 30 Oct 2025).
Gate Durations: Gate duration is approximately 5–10 μs for single-qubit and 200–400 μs for two-qubit gates, with overall circuit depths managed to avoid excessive decoherence (Karacan, 26 Nov 2025, Hémery et al., 2023).
SPAM and Crosstalk: State preparation and measurement (SPAM) errors are typically 1×10⁻³ or less; measurement crosstalk is measured at or below 3×10⁻⁶ (Alam et al., 30 Oct 2025).

3. Performance Metrics and Circuit Capabilities

Quantitative performance metrics are determined by practical benchmarks and experimental calibration:

Metric	H2-1/H2-2 Quoted Value	Reference
Qubit count (tested/maximum)	56/∼70	(Alam et al., 30 Oct 2025)
Single-qubit gate error	3×10⁻⁵	(Alam et al., 30 Oct 2025)
Two-qubit gate error	1×10⁻³ (∼99.90% fidelity)	(Alam et al., 30 Oct 2025)
Circuit depth-10 random-circuit φ	≳0.30	(Liu et al., 26 Mar 2025)
SPAM error	∼0.1%	(Hémery et al., 2023, Alam et al., 30 Oct 2025)
Coherence times	T₁ > 30 s, T₂* ∼ 1 s, T₂ > 10 s	(Alam et al., 30 Oct 2025)

Typical digital quantum circuits executed reach several thousand native two-qubit gates per shot: e.g., 2415 two-qubit gates per Trotter step in fermionic simulation; random-circuit sampling with 10 layers of two-qubit gates; phase estimation with 184–414 two-qubit gates using compressed controlled evolution (Liu et al., 26 Mar 2025, Karacan, 26 Nov 2025, Alam et al., 30 Oct 2025).

4. Compilation, Circuit Optimizations, and Run-Time Strategies

The H2 system applies a range of circuit optimizations, tailored to its all-to-all connectivity and high-fidelity operations:

Native Compilation: Circuits are directly decomposed into the device's native SU(2) and ZZPhase gates. No further gate decomposition is required beyond the hardware-native gate set (Liu et al., 26 Mar 2025).
Compiler Optimization: Use of advanced compilers (e.g., pytket with FullPeepholeOptimise()) merges consecutive one-qubit gates and exploits all-to-all connectivity to avoid physically realized SWAPs (Alam et al., 30 Oct 2025, Hémery et al., 2023).
Logical SWAPs: Relabeling rather than physical execution eliminates the overhead of routing qubits, essential for efficiently simulating periodic boundary conditions or nonlocal interactions (Alam et al., 30 Oct 2025).
Job Scheduling and Prechecks: Batch execution includes device-readiness prechecks (e.g., cooling and calibration) and post-selection by latency (discarding shots exceeding execution time cutoffs) to ensure optimal circuit operation (Liu et al., 26 Mar 2025).

5. Error Characterization, Suppression, and Mitigation

Comprehensive error characterization and mitigation are crucial for scaling circuit depth and fidelity:

Error Characterization: The dominant errors are two-qubit gate coherent over-rotations, depolarizing/dephasing single-qubit errors, SPAM, and measurement crosstalk (Alam et al., 30 Oct 2025, Hémery et al., 2023).
Pauli Twirling / Pseudo-Twirling: Each two-qubit R_{zz}(θ) gate is conjugated by random two-qubit Pauli operators, randomizing coherent errors into stochastic channels (Alam et al., 30 Oct 2025, Karacan, 26 Nov 2025). For phase estimation, Pauli-twirled error models support amplitude renormalization-based error bar protocols.
Error-Mitigation Protocols: Multiple methods are applied:
- TFLO (Training with Fermionic Linear Optics): Fits measurement outcomes for exactly simulable (U=0) circuits, then extrapolates to interacting cases (Alam et al., 30 Oct 2025).
- TMPS: Training using short-time tensor-network (MPS) data for extrapolation to longer times and higher-weight observables (Alam et al., 30 Oct 2025).
- Global-Fidelity Rescaling: For Loschmidt amplitude measurement, observed amplitude is globally rescaled by the predicted circuit fidelity $q = \prod_i F_{2q,i}$ (Hémery et al., 2023).
- Zero-Noise Extrapolation (ZNE): Circuit folding and output extrapolation techniques to separate out depolarizing and cross-talk errors (Hémery et al., 2023).
- Gaussian Process Regression: Smoothing of time-series output to reduce noise while preserving signal correlations (Alam et al., 30 Oct 2025).
Shot Constraints: Slower shot rates (∼5 s/shot for 56–qubit circuits) and limited shot budgets necessitate advanced mitigation, as aggressive simple averaging is infeasible (Alam et al., 30 Oct 2025).

6. Benchmarks: Quantum Randomness, Simulation, and Phase Estimation

The platform has enabled several milestone quantum information processing demonstrations:

Certified Randomness: Generation of 71,313 certified random bits in a single experiment, achieved via random circuit sampling, cross-entropy benchmarking (XEB), and a rigorous adversary model. Circuit randomization, strict timing cutoffs, and direct classical hardness arguments underpin the entropy certification protocol (Liu et al., 26 Mar 2025).
Fermionic Dynamics: Digital simulation of a 56-qubit 2D Fermi-Hubbard model through Trotterized evolution (∼10,000 two-qubit gates per circuit), with cross-validated spin-charge separation and Wilson-loop observables beyond the reach of classical tensor methods (Alam et al., 30 Oct 2025).
Loschmidt Amplitude Measurement: GHZ-based digital interferometry measuring the Loschmidt amplitude for 32-qubit Fermi-Hubbard circuits (254 two-qubit gates per Trotter evolution), with SPAM, post-selection, and zero-noise extrapolation for error mitigation (Hémery et al., 2023).
Quantum Phase Estimation: Implementation of iterative quantum phase estimation (IQPE) on spin-lattice models using a compressed control protocol (TICC), achieving sub-1% ground-state energy errors with <200 hardware-native two-qubit gates, and demonstrating scaling advantages from control overhead compression (Karacan, 26 Nov 2025).

7. System Constraints, Scalability, and Outlook

While the Quantinuum H2 architecture delivers exceptional circuit fidelities and full connectivity, system-level constraints remain:

Depth and Fidelity Limitations: Execution depth is bounded by accumulation of gate errors and memory decoherence; e.g., for 56-qubit Fermi-Hubbard simulation, meaningful dynamics were observed up to $t \lesssim 1.5$ (four Trotter steps, ∼10,000 two-qubit gates) (Alam et al., 30 Oct 2025).
Scaling Overheads: Signal damping from two-qubit error rates (e.g., $F_{2q} \sim 0.998$ ) drives exponential shot overhead for large systems; for a 6×6 lattice, shot requirements for high-fidelity estimation become impractically large without further hardware improvement or algorithmic optimization (Hémery et al., 2023).
Mitigation Frontier: Hardware advances in gate fidelity (pushing $F_{2q}$ towards 0.999+) and further algorithmic advances are required for intractable many-body simulation at larger scales or greater depths (Hémery et al., 2023).

A plausible implication is that the all-to-all connectivity and progressive error mitigation strategies position the H2 platform at or near the threshold for quantum simulation tasks that surpass exact classical capability, with near-term gains predicated on both hardware and compiler improvements. The system has established digital trapped-ion QCs as a central tool in quantum simulation and quantum-certified cryptographic primitives (Liu et al., 26 Mar 2025, Alam et al., 30 Oct 2025, Karacan, 26 Nov 2025, Hémery et al., 2023).